Datasheet TB9084FTG (Toshiba) - 9

link to page 49 link to page 9 link to page 49 link to page 40 TB9084FTG <High-side drive circuit, Low-side drive circuit> A high-side drive circuit drives a high-side 3-phase FET. A low-side drive circuit drives a low-side 3-phase FET. This product is equipped with 3 channels of high-side and low-side circuits each. Input signals (HUI/HVI/HWI, LUI/LVI/LWI) are converted in the control block to generate output signals (HUO/HVO/HWO, LUO/LVO/LWO). Current Limit Function To protect this product from a short to power or ground, electric current of high-side drive and low-side drive circuits after a turn-on/turn-off is switched to a limited current (Io_lmth/Io_lmtl) after a set time “t_ilim” (“000” to “111”) of CONFIG4 register. Prohibited Input Detection Note: “*” means u, v and w or U, V and W. This function is to prevent through-current from being generated by both upper and lower FETs in the same phase being turned on by an input signal. The truth table is shown in Table 7.2.1.1. The behavior when H*I=L*I="H" regardless of the period when the gate driver is enabled or disable (gate_en_*="H" or "L") can be selected by pl_op register in CONFIG4. When pl*_dis bit is “L,” the input prohibition mode is enabled and the output is H*O=L*O=“L.” At this time, whether the status register is set to “H” or NDIAG=“L” can be selected by pl_op. When pl_op is set to “H,” set err_pl_* to “H.” When pl_op=“L,” do not set err_pl_* to “H.” NDIAG terminal follows the status register. To turn off a gate driver circuit for driving a 3-phase FET (6ch), drive the gate driver to “L” so that the FET that drives the motor is turned off. Turning off a gate driver circuit for driving a 3-phase FET (2ch) of a detected phase means driving the gate driver to “L” so that the H/L part FET of the detected phase is turned off. When pl*_dis=“H,” detection of prohibited input itself is disabled, and the output can be H*O=L*O=“H” For details of the internal signals (gate_en_*) in the truth table, see chapter 7.7.
Table 7.2.1.1 I/O Truth Table (High-side, Low-side drive circuits)
FET Drive Circuit( “*” means u, v and w or U, V and W ) Internal Register Signal Input Output Setting status Remarks (gate_en_*) H*I L*I pl*_dis pl_op H*O L*O err_pl_* “L” X X X - Inactive X “L” X X - “L” “0” “0” “L” “L” - Prohibited Input Mode, Without Status “H” “H” “0” “1” “set” Prohibited Input Mode, With Status “1” X - Prohibited Input Mode Disabled (U phase) “L” “L” X X “L” “L” - “L” “H” X X “L” “H” - Active “H” “L” X X “H” “L” - “H” “0” “0” “L” “L” - Prohibited Input Mode, Without Status “H” “H” “0” “1” “L” “L” “set” Prohibited Input Mode, With Status “1” X “H” “H” - Prohibited Input Mode Disabled (U phase) Note: X means “Don’t care” Note: NDIAG terminal is linked with the status. The status can be cleared by setting err_pl_*_cl bit. © 2 025 9 2025-07-31 Toshiba Electronic Devices & Storage Corporation Rev. 3.0 Document Outline 1. Description 2. Applications 3. Features 4. Block Diagram 5. Pin Assignments Top view 6. Pin Description 7. Functional Description 7.1. Charge Pump Circuit 7.2. Gate Driver Circuits 7.2.1. Gate Drivers for Driving 3-Phase FETs 7.2.2. Gate Driver for FET for Reverse Polarity Protection 7.3. Current Sensing Circuit 7.3.1. Configuration 7.3.2. Offset Calibration 7.4. Oscillation Circuit 7.5. Abnormality Flag Output Function 7.5.1. NDIAG Terminal Output 7.5.2. Status Registers in SPI communication 7.6. Abnormality Detection Circuits 7.6.1. VCC Under Voltage Detection Function 7.6.2. VB Under Voltage Detection Function 7.6.3. RPPO Under Voltage Detection Function 7.6.4. VCC Over Voltage Detection Function 7.6.5. VCP Over Voltage Detection Function 7.6.6. Over temperature Detection Function 7.6.7. VDS Detection Function for 3-Phase FETs 7.6.8. Abnormality Detection for CP1SW and CP2SW Terminals 7.7. Alarm Input Circuit 7.8. SPI Communication Circuit 7.8.1. SPI Communication Operation 7.8.2. Error Judgment 7.8.3. Register Map 7.8.3.1. CONFIG1 Write Address=2h / Read Address=3h 7.8.3.2. CONFIG2 Write Address=4h / Read Address=5h 7.8.3.3. CONFIG3 Write Address=6h / Read Address=7h 7.8.3.4. CONFIG4 (Write Address=8h / Read Address=9h 7.8.3.5. CONFIG5 Write Address=Ah / Read Address=Bh 7.8.3.6. STAT1 / Read Address=Dh 7.8.3.7. STAT2 / Read Address=Fh 7.8.3.8. STAT1_CLR Write Address=10h 7.8.3.9. STAT2_CLR Write Address=12h 7.8.3.10. NOP Write Address=Fh / Read Address=Fh 8. Absolute Maximum Ratings (Ta = 25 C) 9. Electrical Characteristics 9.1. Operating Voltage Ranges 9.2. Consumption Current 9.3. Charge Pump Circuit 9.4. Gate Driver Circuits 9.5. Current Sense Amplifier Circuit 9.6. Oscillation Circuit 9.7. Abnormality Detection Circuits 9.8. Alarm Input Circuit 9.9. SPI Communication Circuit 10. Application Circuit Example 11. Package Outlines 12. Revision History 13. Abbreviation Collection RESTRICTIONS ON PRODUCT USE