Datasheet SN74LVC1G16 (Texas Instruments) - 9

HerstellerTexas Instruments
BeschreibungOne-channel 1.65V-to-5.5V inverter with open-drain outputs and Schmitt-trigger inputs
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SN74LVC1G16. www.ti.com. 9 Detailed Description 9.1 Feature Description 9.1.1 Open-Drain CMOS Outputs

SN74LVC1G16 www.ti.com 9 Detailed Description 9.1 Feature Description 9.1.1 Open-Drain CMOS Outputs

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SN74LVC1G16 www.ti.com
SCLSA29B – OCTOBER 2024 – REVISED MAY 2025
9 Detailed Description 9.1 Feature Description 9.1.1 Open-Drain CMOS Outputs
This device includes open-drain CMOS outputs. Open-drain outputs can only drive the output low. When in the high logical state, open-drain outputs will be in a high-impedance state. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. When placed into the high-impedance state, the output will neither source nor sink current, with the exception of minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to the node, then this is known as a floating node and the voltage is unknown. A pull-up resistor can be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations. Typically, a 10kΩ resistor can be used to meet these requirements. Unused open-drain CMOS outputs should be left disconnected.
9.1.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics table, using Ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
9.1.3 Clamp Diode Structure
Figure 9-1 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74LVC1G16 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information 5.5 Electrical Characteristics 5.6 Switching Characteristics 5.7 Typical Characteristics 6 Parameter Measurement Information 7 Overview 8 Functional Block Diagram 9 Detailed Description 9.1 Feature Description 9.1.1 Open-Drain CMOS Outputs 9.1.2 CMOS Schmitt-Trigger Inputs 9.1.3 Clamp Diode Structure 10 Application and Implementation 10.1 Application Information 10.2 Typical Application 10.2.1 Design Requirements 10.2.1.1 Power Considerations 10.2.1.2 Input Considerations 10.2.1.3 Output Considerations 10.2.2 Detailed Design Procedure 10.3 Application Curves 10.4 Power Supply Recommendations 10.5 Layout 10.5.1 Layout Guidelines 10.5.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Revision History 13 Mechanical, Packaging, and Orderable Information