Datasheet 74AC169 (Fairchild) - 2

Functional Description Mode Select Table
The AC169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input
Action on Rising 74AC169 PE CEP CET U/D
signals in either state of the Clock. The only requirement is
Clock Edge
that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain L X X X Load (Pn to Qn) valid for the recommended hold time thereafter. The paral- H L L H Count Up (Increment) lel load operation takes precedence over the other opera- tions, as indicated in the Mode Select Table. When PE is H L L L Count Down (Decrement) LOW, the data on the P0–P3 inputs enters the flip-flops on H H X X No Change (Hold) the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be H X H X No Change (Hold) HIGH; the U/D input then determines the direction of count- H = HIGH Voltage Level ing. The Terminal Count (TC) output is normally HIGH and L = LOW Voltage Level goes LOW, provided that CET is LOW, when a counter X = Immaterial reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of
State Diagram
the Count Enable Parallel (CEP) input level. If an illegal state occurs, the AC169 will return to the legitimate sequence within two counts. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below). 1. Count Enable = CEP •CET • PE 2. Up: TC = Q0•Q1•Q 2Q3•(Up)•CET 3. Down: TC = Q0• Q1•Q2•Q3 •(Down)•CET
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2