Datasheet MAX5362 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package |
| Seiten / Seite | 13 / 8 — Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 … |
| Dateiformat / Größe | PDF / 214 Kb |
| Dokumentensprache | Englisch |
Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package. Table 1. Unipolar Code Current. DAC CODE
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Textversion des Dokuments
Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package
VDD VREF CURRENT- OUT REF STEERING DAC 255 SW1 SW2 SW255 SDA DATA LATCH MAX5360 CONTROL 6 + 2 MAX5361 10k SCL LOGIC MAX5362 SERIAL INPUT OUT REGISTER GND Figure 1. Functional Diagram Figure 2. Current-Steering Topology
Table 1. Unipolar Code Current DAC CODE OUTPUT VOLTAGE 6 BITS + 2 SUBBITS MAX5360 MAX5361 MAX5362
111111 (00) 2V (63/64) 4V (63/64) 0.9 VDD (63/64) 100000 (00) 1V 2V 0.9 VDD / 2
MAX5360/MAX5361/MAX5362
000001 (00) 31mV 62mV 0.9 VDD / 64 000000 (00) 0 0 0
Detailed Description
current is then converted to a voltage across a resistor, and this voltage is buffered by the output buffer amplifier. The MAX5360/MAX5361/MAX5362 voltage-output, 6-bit DACs offer full 6-bit performance with less than 1LSB
Output Voltage
integral nonlinearity (INL) error and less than 1LSB dif- Table 1 shows the relationship between the DAC code ferential nonlinearity (DNL) error ensuring monotonic and the analog output voltage. The 6-bit DAC code is performance. The devices use a simple two-wire, fast- binary unipolar with 1LSB = (VREF / 64). The MAX5360/ mode I2C-compatible serial interface that operates up MAX5361 have a full-scale output voltage of (+2V - to 400kHz. The MAX5360/MAX5361/MAX5362 include 1LSB) and (+4V - 1LSB), respectively, set by the inter- an internal reference, an output buffer, and low-current nal references. The MAX5362 has a full-scale output shutdown mode, making them ideal for low-power, voltage of (0.9 VDD - 1LSB). Each device accepts 8-bit highly integrated applications. Figure 1 shows the DAC codes, but the accuracy is guaranteed only for devices’ functional diagram. 6 bits.
Analog Section Output Buffer
The MAX5360/MAX5361/MAX5362 employ a current- The DAC voltage output is an internally buffered unity- steering DAC topology as shown in Figure 2. At the gain follower that typically slews at ±0.4V/µs. The out- core of the DAC is a reference voltage-to-current con- put can swing from 0 to full scale. With a 1/4 FS to 3/4 verter (V/I) that generates a reference current. This cur- FS output transition, the amplifier outputs typically settle rent is mirrored to 255 equally weighted current to 1/2LSB in less than 5µs when loaded with 10kΩ in sources. DAC switches control the outputs of these cur- parallel with 50pF. The buffer amplifiers are stable with rent mirrors, so only the desired fraction of the total cur- any combination of resistive loads >10kΩ and capaci- rent-mirror currents is steered to the DAC output. The tive loads <50pF.
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VDD VREF CURRENT- OUT REF STEERING DAC 255 SW1 SW2 SW255 SDA DATA LATCH MAX5360 CONTROL 6 + 2 MAX5361 10k SCL LOGIC MAX5362 SERIAL INPUT OUT REGISTER GND Figure 1. Functional Diagram Figure 2. Current-Steering Topology
Table 1. Unipolar Code Current DAC CODE OUTPUT VOLTAGE 6 BITS + 2 SUBBITS MAX5360 MAX5361 MAX5362
111111 (00) 2V (63/64) 4V (63/64) 0.9 VDD (63/64) 100000 (00) 1V 2V 0.9 VDD / 2
MAX5360/MAX5361/MAX5362
000001 (00) 31mV 62mV 0.9 VDD / 64 000000 (00) 0 0 0
Detailed Description
current is then converted to a voltage across a resistor, and this voltage is buffered by the output buffer amplifier. The MAX5360/MAX5361/MAX5362 voltage-output, 6-bit DACs offer full 6-bit performance with less than 1LSB
Output Voltage
integral nonlinearity (INL) error and less than 1LSB dif- Table 1 shows the relationship between the DAC code ferential nonlinearity (DNL) error ensuring monotonic and the analog output voltage. The 6-bit DAC code is performance. The devices use a simple two-wire, fast- binary unipolar with 1LSB = (VREF / 64). The MAX5360/ mode I2C-compatible serial interface that operates up MAX5361 have a full-scale output voltage of (+2V - to 400kHz. The MAX5360/MAX5361/MAX5362 include 1LSB) and (+4V - 1LSB), respectively, set by the inter- an internal reference, an output buffer, and low-current nal references. The MAX5362 has a full-scale output shutdown mode, making them ideal for low-power, voltage of (0.9 VDD - 1LSB). Each device accepts 8-bit highly integrated applications. Figure 1 shows the DAC codes, but the accuracy is guaranteed only for devices’ functional diagram. 6 bits.
Analog Section Output Buffer
The MAX5360/MAX5361/MAX5362 employ a current- The DAC voltage output is an internally buffered unity- steering DAC topology as shown in Figure 2. At the gain follower that typically slews at ±0.4V/µs. The out- core of the DAC is a reference voltage-to-current con- put can swing from 0 to full scale. With a 1/4 FS to 3/4 verter (V/I) that generates a reference current. This cur- FS output transition, the amplifier outputs typically settle rent is mirrored to 255 equally weighted current to 1/2LSB in less than 5µs when loaded with 10kΩ in sources. DAC switches control the outputs of these cur- parallel with 50pF. The buffer amplifiers are stable with rent mirrors, so only the desired fraction of the total cur- any combination of resistive loads >10kΩ and capaci- rent-mirror currents is steered to the DAC output. The tive loads <50pF.
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