Datasheet MCP6C02 (Microchip) - 5

link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 5 link to page 37 link to page 37 link to page 5
MCP6C02 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings †
VDD – VSS .. -0.3V to +5.5V Current at Input Pins (Note 1) ...±2 mA Analog Inputs (VIP and VIM) (Note 1) .. -0.3V to +70V All Other Inputs and Outputs...VSS – 0.3V to VDD + 0.3V Input Difference Voltage (VDM) (Note 1) ..±1.2V Output Short-Circuit Current ... Continuous Current at Output and Supply Pins ...±30 mA Storage Temperature ..-65°C to +150°C Maximum Junction Temperature (Note 2) ... +155°C ESD protection (HBM, CDM, MM) ... ≥ 2 kV, 2 kV, 300V
† Notice:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability.
Note 1:
These voltage and current ratings are physically independent; each required condition must be enforced by the user (see
Section 5.1.2 “Input Voltage Limits”
and
Section 5.1.3 “Input Current Limits”
).
2:
The Absolute Maximum Junction Temperature is not intended for continuous use.
1.2 Voltage and Temperature Ranges
The various voltage and temperature ranges are listed in Table 1-1.
TABLE 1-1: VOLTAGE AND TEMPERATURE RANGES Range Parameter Units GDM (V/V) Comment Type Sym. Spec. Oper. Abs. Min./Max.
VDD V Al VDD ↑ Min. VDDL 2.0 1.7 -0.3 (Note 2) (LV POR on) LV POR VPLH – 0.1 Typ. — — Hysteresis VPLH — Typ. — 2.0 to 5.5 — — Max. VDDH 5.5 5.5 5.5 VIP V Al VIP ↑ Min. VIPL 3.0 2.8 -0.3 (Note 2) (HV POR on) VIP ↓ VIPLD 2.8 2.6 (HV POR on) HV POR VIPLH 0.2 Typ. 0.2 Typ. — Hysteresis — Typ. — 34 — — Max. VIPH 65 68 70
Note 1:
All of this table’s limits are set by design and characterization.
2:
The HV POR is triggered by VIP, with hysteresis. The LV POR is triggered by VDD, with hysteresis.
3:
VDM = VIP – VIM. VIM is in its range when both VIP and VDM are in their ranges.
4:
Allowing the ambient temperature (TA) to exceed the Maximum Ambient Temperature limit (TAH) may cause parameters to exceed their specified limits. See
Section 1.1 “Absolute Maximum Ratings †”
for the Absolute Maximum Junction Temperature and Storage Temperature limits.
5:
VOL and VOH are at RL = 1 k  2018-2021 Microchip Technology Inc. DS20006129C-page 5 Document Outline Features Typical Applications Related Products General Description Typical Application Circuit Functional Diagram Gain Options TABLE 1: Key Differentiating Specifications FIGURE 1: Input Offset Voltage vs. Temperature, GDM = 20 V/V. FIGURE 2: Input Offset Voltage vs. Temperature, GDM = 50 V/V. FIGURE 3: Input Offset Voltage vs. Temperature, GDM = 100 V/V. FIGURE 4: CMRR vs. Frequency. 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Voltage and Temperature Ranges TABLE 1-1: Voltage and Temperature Ranges 1.3 Specifications TABLE 1-2: DC Electrical Characteristics TABLE 1-3: AC Electrical Characteristics TABLE 1-4: Temperature Specifications 1.4 Simplified Diagrams FIGURE 1-1: Common-Mode Input Voltage Range vs. Temperature. FIGURE 1-2: Differential Input Voltage Range vs. Temperature. FIGURE 1-3: Reference Voltage Range vs. Temperature. FIGURE 1-4: Common-Mode Input Overdrive Recovery Timing Diagram. FIGURE 1-5: Differential-Mode Input Overdrive Recovery Timing Diagram. FIGURE 1-6: Output Overdrive Recovery Timing Diagram. FIGURE 1-7: VOUT Power On/Off Timing Diagram, Low-Side. FIGURE 1-8: VOUT Power On/Off Timing Diagram, High-Side. 1.5 Simplified Test Circuits FIGURE 1-9: Input Offset Test Circuit for the MCP6C02. EQUATION 1-1: EQUATION 1-2: FIGURE 1-10: Differential Gain Test Circuit. FIGURE 1-11: AC Gain Test Circuit. 1.6 Explanation of DC Error Specifications EQUATION 1-3: EQUATION 1-4: EQUATION 1-5: TABLE 1-5: Exponential Term EQUATION 1-6: FIGURE 1-12: Input Offset Error vs. Common-Mode Input Voltage. EQUATION 1-7: EQUATION 1-8: EQUATION 1-9: FIGURE 1-13: Differential Input Error vs. Differential Input Voltage. EQUATION 1-10: EQUATION 1-11: 2.0 Typical Performance Curves 2.1 DC Precision FIGURE 2-1: Input Offset Voltage, GDM = 20. FIGURE 2-2: Input Offset Voltage, GDM = 50. FIGURE 2-3: Input Offset Voltage, GDM = 100. FIGURE 2-4: Linear Input Offset Voltage Drift, GDM = 20. FIGURE 2-5: Linear Input Offset Voltage Drift, GDM = 50. FIGURE 2-6: Linear Input Offset Voltage Drift, GDM = 100. FIGURE 2-7: Quadratic Input Offset Voltage Drift, GDM = 20. FIGURE 2-8: Quadratic Input Offset Voltage Drift, GDM = 50. FIGURE 2-9: Quadratic Input Offset Voltage Drift, GDM = 100. FIGURE 2-10: Exponential Input Offset Voltage Drift, GDM = 20. FIGURE 2-11: Exponential Input Offset Voltage Drift, GDM = 50. FIGURE 2-12: Exponential Input Offset Voltage Drift, GDM = 100. FIGURE 2-13: Input Offset Voltage vs. Power Supply Voltage, with GDM = 20. FIGURE 2-14: Input Offset Voltage vs. Power Supply Voltage, with GDM = 50. FIGURE 2-15: Input Offset Voltage vs. Power Supply Voltage, with GDM = 100. FIGURE 2-16: Input Offset Voltage vs. Common-Mode Input Voltage, with GDM = 20. FIGURE 2-17: Input Offset Voltage vs. Common-Mode Input Voltage, with GDM = 50. FIGURE 2-18: Input Offset Voltage vs. Common-Mode Input Voltage, with GDM = 100. FIGURE 2-19: Input Offset Voltage vs. Reference Voltage, with GDM = 20. FIGURE 2-20: Input Offset Voltage vs. Reference Voltage, with GDM = 50. FIGURE 2-21: Input Offset Voltage vs. Reference Voltage, with GDM = 100. FIGURE 2-22: 1/CMRR, with GDM = 20. FIGURE 2-23: 1/CMRR, with GDM = 50. FIGURE 2-24: 1/CMRR, with GDM = 100. FIGURE 2-25: 1/PSRR, with GDM = 20. FIGURE 2-26: 1/PSRR, with GDM = 50. FIGURE 2-27: 1/PSRR, with GDM = 100. FIGURE 2-28: CMRR vs. Ambient Temperature. FIGURE 2-29: PSRR vs. Ambient Temperature. FIGURE 2-30: Input Offset Voltage - Final Test Results. FIGURE 2-31: PSRR - Final Test Results. FIGURE 2-32: CMRR - Final Test Results. FIGURE 2-33: Gain Error. FIGURE 2-34: Gain Error Temperature Drift. FIGURE 2-35: Differential Gain Nonlinearity. 2.2 Other DC Voltages and Currents FIGURE 2-36: VIP Pin Input Bias Current vs. Input Common-Mode Voltage. FIGURE 2-37: VIM Pin Input Bias Current vs. Input Common-Mode Voltage, VDM = VDML. FIGURE 2-38: VIM Pin Input Bias Current vs. Input Common-Mode Voltage, VDM = VDMH. FIGURE 2-39: VIP Pin Input Bias Current vs. Ambient Temperature. FIGURE 2-40: VIM Pin Input Bias Current vs. Ambient Temperature. FIGURE 2-41: VIM Pin Input Bias Current vs. Differential Input Voltage. FIGURE 2-42: Input Bias Current vs. Input Common-Mode Voltage (below VSS). FIGURE 2-43: Common-Mode Input Range vs. Ambient Temperature. FIGURE 2-44: Reference Voltage Range vs. Ambient Temperature. FIGURE 2-45: Minimum Rise or Fall Time vs. Common Mode Input Step. FIGURE 2-46: Output Voltage Range vs. Output Current. FIGURE 2-47: Output Voltage Range vs. Ambient Temperature. FIGURE 2-48: Supply Current vs. Power Supply Voltage. FIGURE 2-49: Output Short Circuit Current vs. Power Supply Voltage for E-Temp Parts. FIGURE 2-50: Output Short Circuit Current vs. Power Supply Voltage for H-Temp Parts. FIGURE 2-51: LV POR (for VDD) Trip Points vs. Ambient Temperature. FIGURE 2-52: HV POR (for VIP) Trip Points vs. Ambient Temperature. 2.3 Frequency Response FIGURE 2-53: Gain vs. Frequency, with Capacitive Load. FIGURE 2-54: CMRR vs. Frequency. FIGURE 2-55: PSRR vs. Frequency. FIGURE 2-56: Closed-Loop Output Impedance Magnitude vs. Frequency. FIGURE 2-57: EMI Rejection Ratio vs. Frequency. FIGURE 2-58: EMI Rejection Ratio vs. Signal Strength. 2.4 Noise and Intermodulation Distortion FIGURE 2-59: Input Noise Voltage Density vs. Frequency. FIGURE 2-60: Input Noise Voltage vs. Frequency. FIGURE 2-61: Intermodulation Distortion vs. Frequency, with VDD Disturbance. FIGURE 2-62: Input Noise Voltage vs. Time, GDM = 20. FIGURE 2-63: Input Noise Voltage vs. Time, GDM = 50. FIGURE 2-64: Input Noise Voltage vs. Time, GDM = 100. 2.5 Time Response FIGURE 2-65: Input Offset Voltage vs. Time, with Temperature Change. FIGURE 2-66: Input Offset Voltage vs. Time, at Power-Up. FIGURE 2-67: The MCP6C02 Shows No Phase Reversal vs. Differential Input Overdrive. FIGURE 2-68: The MCP6C02 Shows No Phase Reversal vs. Input Common-Mode Overdrive. FIGURE 2-69: Small Signal Step Response to Differential Input Voltage. FIGURE 2-70: Small Signal Step Response to Common-Mode Input Voltage. FIGURE 2-71: Small Signal Step Response to Differential Input Voltage, with Capacitive Load (CL). FIGURE 2-72: Small Signal Step Response Overshoot, with Capacitive Load (CL). FIGURE 2-73: Small Signal Step Response Rise Time, with Capacitive Load (CL). FIGURE 2-74: Small Signal Step Response Settling Time, with Capacitive Load (CL). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Noninverting Analog Signal Input (VIP) 3.2 Inverting Analog Signal Input (VIM) 3.3 Analog Output Reference Voltage (VREF) 3.4 Analog Output (VOUT) 3.5 Low-Side Power Supplies (VDD, VSS) 3.6 Exposed Pad (EP) 4.0 Device Operation 4.1 Basic Performance EQUATION 4-1: FIGURE 4-1: Basic Circuit. FIGURE 4-2: MCP6C02 Block Diagram. EQUATION 4-2: EQUATION 4-3: EQUATION 4-4: FIGURE 4-3: DC Bias Resistors and Currents. EQUATION 4-5: EQUATION 4-6: EQUATION 4-7: 4.2 Overview of Zero-Drift Operation FIGURE 4-4: MCP6C02 Block Diagram. FIGURE 4-5: First Chopping Clock Phase; Simplified Diagram. FIGURE 4-6: Second Chopping Clock Phase; Simplified Diagram. 4.3 Internal Protection FIGURE 4-7: Input Protection for VDM (i.e., for VIM) and VIP – VSS. FIGURE 4-8: Input Protection for VREF, VOUT and VDD. 5.0 Applications 5.1 Recommended Design Practices FIGURE 5-1: Protecting VIP. FIGURE 5-2: Protecting VDM with Diodes. FIGURE 5-3: Protecting VDM with a Filter at VIM. FIGURE 5-4: Protection for Capacitive Loads. FIGURE 5-5: Protection for Motor Loads. EQUATION 5-1: FIGURE 5-6: PCB Layout for RSH (connections to VIP and VIM). EQUATION 5-2: EQUATION 5-3: FIGURE 5-7: VREF Bypass Circuit #1. FIGURE 5-8: VREF Bypass Circuit #2. FIGURE 5-9: Recommended RISO Values for Capacitive Loads. FIGURE 5-10: Bandwidth and Gain Peaking vs. Capacitive Load, without RISO. FIGURE 5-11: Recommended RISO vs. Capacitive Load. FIGURE 5-12: SNR vs. Bandwidth Estimates, VDD = 2.0V. FIGURE 5-13: SNR vs. Bandwidth Estimates, VDD = 5.5V. 5.2 Typical Application Circuits FIGURE 5-14: Simplified Motor Current Monitor for Regulated Supply Voltage. FIGURE 5-15: H-Bridge Motor Current Monitor, With a Few Possible Monitor Locations. FIGURE 5-16: Analog Level Shifter. 6.0 Packaging Information 6.1 Package Marking Information Zero-Drift, 65V High-Side Current Sense Amplifier Appendix A: Revision History Revision C (January 2021) Revision B (September 2019) Revision A (November 2018) Appendix B: Offset Test Screens TABLE B-1: Offset Test Screens Product Identification System Worldwide Sales and Service