Datasheet EFM8SB1 (Silicon Labs) - 9
| Hersteller | Silicon Labs |
| Beschreibung | EFM8 Sleepy Bee Family |
| Seiten / Seite | 71 / 9 — Serial Peripheral Interface (SPI0). System Management Bus / I2C (SMB0). … |
| Dateiformat / Größe | PDF / 1.2 Mb |
| Dokumentensprache | Englisch |
Serial Peripheral Interface (SPI0). System Management Bus / I2C (SMB0). 16-bit CRC (CRC0). silabs.com
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EFM8SB1 Data Sheet System Overview
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. The SPI module includes the following features: • Supports 3- or 4-wire operation in master or slave modes. • Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode. • Support for four clock phase and polarity options. • 8-bit dedicated clock clock rate generator. • Support for multiple masters on the same data lines.
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica- tion, version 1.1, and compatible with the I2C serial bus. The SMBus module includes the following features: • Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds. • Support for master, slave, and multi-master modes. • Hardware synchronization and arbitration for multi-master mode. • Clock low extending (clock stretching) to interface with faster masters. • Hardware support for 7-bit slave and general call address recognition. • Firmware support for 10-bit slave address decoding. • Ability to inhibit all slave states. • Programmable data setup/hold times.
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the flash contents of the device. The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features: • Support for CCITT-16 polynomial • Byte-level bit reversal • Automatic CRC of flash contents on one or more 256-byte blocks • Initial seed selection of 0x0000 or 0xFFFF
silabs.com
| Building a more connected world. Rev. 1.4 | 8 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Capacitive Sense (CS0) 4.1.15 Port I/O 4.1.16 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB1x-QFN20 Pin Definitions 6.2 EFM8SB1x-QFN24 Pin Definitions 6.3 EFM8SB1x-QSOP24 Pin Definitions 6.4 EFM8SB1x-CSP16 Pin Definitions 7. CSP16 Package Specifications 7.1 CSP16 Package Dimensions 7.2 CSP16 PCB Land Pattern 7.3 CSP16 Package Marking 8. QFN20G Package Specifications 8.1 QFN20 Package Dimensions 8.2 QFN20 PCB Land Pattern 8.3 QFN20 Package Marking 9. QFN20A Package Specifications 9.1 QFN20 Package Dimensions 9.2 QFN20 PCB Land Pattern 9.3 QFN20 Package Marking 10. QFN24 Package Specifications 10.1 QFN24 Package Dimensions 10.2 QFN24 PCB Land Pattern 10.3 QFN24 Package Marking 11. QSOP24 Package Specifications 11.1 QSOP24 Package Dimensions 11.2 QSOP24 PCB Land Pattern 11.3 QSOP24 Package Marking 12. Revision History 12.1 Revision 1.4 12.2 Revision 1.3 12.3 Revision 1.2 12.4 Revision 1.1 Table of Contents
Serial Peripheral Interface (SPI0)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional general purpose port I/O pins can be used to select multiple slave devices in master mode. The SPI module includes the following features: • Supports 3- or 4-wire operation in master or slave modes. • Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode. • Support for four clock phase and polarity options. • 8-bit dedicated clock clock rate generator. • Support for multiple masters on the same data lines.
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specifica- tion, version 1.1, and compatible with the I2C serial bus. The SMBus module includes the following features: • Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds. • Support for master, slave, and multi-master modes. • Hardware synchronization and arbitration for multi-master mode. • Clock low extending (clock stretching) to interface with faster masters. • Hardware support for 7-bit slave and general call address recognition. • Firmware support for 10-bit slave address decoding. • Ability to inhibit all slave states. • Programmable data setup/hold times.
16-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit polynomial. CRC0 accepts a stream of 8-bit data and posts the 16-bit result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC the flash contents of the device. The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC module supports the standard CCITT-16 16-bit polynomial (0x1021), and includes the following features: • Support for CCITT-16 polynomial • Byte-level bit reversal • Automatic CRC of flash contents on one or more 256-byte blocks • Initial seed selection of 0x0000 or 0xFFFF
silabs.com
| Building a more connected world. Rev. 1.4 | 8 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Power 3.3 I/O 3.4 Clocking 3.5 Counters/Timers and PWM 3.6 Communications and Other Digital Peripherals 3.7 Analog 3.8 Reset Sources 3.9 Debugging 3.10 Bootloader 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Recommended Operating Conditions 4.1.2 Power Consumption 4.1.3 Reset and Supply Monitor 4.1.4 Flash Memory 4.1.5 Power Management Timing 4.1.6 Internal Oscillators 4.1.7 Crystal Oscillator 4.1.8 External Clock Input 4.1.9 ADC 4.1.10 Voltage Reference 4.1.11 Temperature Sensor 4.1.12 Comparators 4.1.13 Programmable Current Reference (IREF0) 4.1.14 Capacitive Sense (CS0) 4.1.15 Port I/O 4.1.16 SMBus 4.2 Thermal Conditions 4.3 Absolute Maximum Ratings 4.4 Typical Performance Curves 5. Typical Connection Diagrams 5.1 Power 5.2 Debug 5.3 Other Connections 6. Pin Definitions 6.1 EFM8SB1x-QFN20 Pin Definitions 6.2 EFM8SB1x-QFN24 Pin Definitions 6.3 EFM8SB1x-QSOP24 Pin Definitions 6.4 EFM8SB1x-CSP16 Pin Definitions 7. CSP16 Package Specifications 7.1 CSP16 Package Dimensions 7.2 CSP16 PCB Land Pattern 7.3 CSP16 Package Marking 8. QFN20G Package Specifications 8.1 QFN20 Package Dimensions 8.2 QFN20 PCB Land Pattern 8.3 QFN20 Package Marking 9. QFN20A Package Specifications 9.1 QFN20 Package Dimensions 9.2 QFN20 PCB Land Pattern 9.3 QFN20 Package Marking 10. QFN24 Package Specifications 10.1 QFN24 Package Dimensions 10.2 QFN24 PCB Land Pattern 10.3 QFN24 Package Marking 11. QSOP24 Package Specifications 11.1 QSOP24 Package Dimensions 11.2 QSOP24 PCB Land Pattern 11.3 QSOP24 Package Marking 12. Revision History 12.1 Revision 1.4 12.2 Revision 1.3 12.3 Revision 1.2 12.4 Revision 1.1 Table of Contents