Datasheet MC74VHC04 (ON Semiconductor) - 6
| Hersteller | ON Semiconductor |
| Beschreibung | Hex Inverter |
| Seiten / Seite | 7 / 6 — PACKAGE DIMENSIONS. TSSOP−14 WB. SCALE 2:1. 14X REF. 2X L/2. −U−. PIN 1. … |
| Revision | 7 |
| Dateiformat / Größe | PDF / 245 Kb |
| Dokumentensprache | Englisch |
PACKAGE DIMENSIONS. TSSOP−14 WB. SCALE 2:1. 14X REF. 2X L/2. −U−. PIN 1. IDENT. DETAIL E. MILLIMETERS. INCHES. DIM MIN. MAX. MIN. −V−. J J1
Modelllinie für dieses Datenblatt
Textversion des Dokuments
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS TSSOP−14 WB
CASE 948G 14 ISSUE C DATE 17 FEB 2016 1
SCALE 2:1 14X REF K
NOTES: 1. DIMENSIONING AND TOLERANCING PER 0.10 (0.004) M T U S V S ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT
N
EXCEED 0.15 (0.006) PER SIDE. 0.25 (0.010)
14 8
4. DIMENSION B DOES NOT INCLUDE
2X L/2
INTERLEAD FLASH OR PROTRUSION.
M
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
B
5. DIMENSION K DOES NOT INCLUDE DAMBAR
L
PROTRUSION. ALLOWABLE DAMBAR
−U− N PIN 1
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F
IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.
1 7
6. TERMINAL NUMBERS ARE SHOWN FOR
DETAIL E
REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. 0.15 (0.006) T U S
K A MILLIMETERS INCHES K1 DIM MIN MAX MIN MAX −V− A
4.90 5.10 0.193 0.200
B
4.30 4.50 0.169 0.177
J J1
ÇÇÇ ÉÉÉ
C
−−− 1.20 −−− 0.047
D
0.05 0.15 0.002 0.006 ÇÇÇ ÉÉÉ
F
0.50 0.75 0.020 0.030
SECTION N−N G
0.65 BSC 0.026 BSC
H
0.50 0.60 0.020 0.024
J
0.09 0.20 0.004 0.008
J1
0.09 0.16 0.004 0.006
−W− C K
0.19 0.30 0.007 0.012
K1
0.19 0.25 0.007 0.010
L
6.40 BSC 0.252 BSC 0.10 (0.004)
M
0 _ 8 _ 0 _ 8 _
−T− SEATING D G H DETAIL E PLANE GENERIC MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX XXXX 7.06 ALYWG G 1 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week 0.65 G = Pb−Free Package PITCH (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. 14X 0.36 14X Pb−Free indicator, “G” or microdot “ G”, 1.26 DIMENSIONS: MILLIMETERS may or may not be present.
DOCUMENT NUMBER: 98ASH70246A
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TSSOP−14 WB PAGE 1 OF 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com
PACKAGE DIMENSIONS TSSOP−14 WB
CASE 948G 14 ISSUE C DATE 17 FEB 2016 1
SCALE 2:1 14X REF K
NOTES: 1. DIMENSIONING AND TOLERANCING PER 0.10 (0.004) M T U S V S ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT
N
EXCEED 0.15 (0.006) PER SIDE. 0.25 (0.010)
14 8
4. DIMENSION B DOES NOT INCLUDE
2X L/2
INTERLEAD FLASH OR PROTRUSION.
M
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
B
5. DIMENSION K DOES NOT INCLUDE DAMBAR
L
PROTRUSION. ALLOWABLE DAMBAR
−U− N PIN 1
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F
IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.
1 7
6. TERMINAL NUMBERS ARE SHOWN FOR
DETAIL E
REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. 0.15 (0.006) T U S
K A MILLIMETERS INCHES K1 DIM MIN MAX MIN MAX −V− A
4.90 5.10 0.193 0.200
B
4.30 4.50 0.169 0.177
J J1
ÇÇÇ ÉÉÉ
C
−−− 1.20 −−− 0.047
D
0.05 0.15 0.002 0.006 ÇÇÇ ÉÉÉ
F
0.50 0.75 0.020 0.030
SECTION N−N G
0.65 BSC 0.026 BSC
H
0.50 0.60 0.020 0.024
J
0.09 0.20 0.004 0.008
J1
0.09 0.16 0.004 0.006
−W− C K
0.19 0.30 0.007 0.012
K1
0.19 0.25 0.007 0.010
L
6.40 BSC 0.252 BSC 0.10 (0.004)
M
0 _ 8 _ 0 _ 8 _
−T− SEATING D G H DETAIL E PLANE GENERIC MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX XXXX 7.06 ALYWG G 1 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week 0.65 G = Pb−Free Package PITCH (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. 14X 0.36 14X Pb−Free indicator, “G” or microdot “ G”, 1.26 DIMENSIONS: MILLIMETERS may or may not be present.
DOCUMENT NUMBER: 98ASH70246A
Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DESCRIPTION: TSSOP−14 WB PAGE 1 OF 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com