Datasheet ADG1406, ADG1407 (Analog Devices) - 9

HerstellerAnalog Devices
Beschreibung9.5 Ω RON, 16-Channel, Differential 8-Channel, ±15 V/+12 V/±5 V iCMOS Multiplexers
Seiten / Seite20 / 9 — Data Sheet. ADG1406/ADG1407. PIN CONFIGURATIONS AND FUNCTION …
RevisionC
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DokumentenspracheEnglisch

Data Sheet. ADG1406/ADG1407. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. 28 D. NC 2. 27 VSS. S16 1. 24 S8. 26 S8. S15 2. 23 S7. S16 4. 25 S7

Data Sheet ADG1406/ADG1407 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 28 D NC 2 27 VSS S16 1 24 S8 26 S8 S15 2 23 S7 S16 4 25 S7

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Data Sheet ADG1406/ADG1407 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS C D S D C C C C S N V N D N N N V V 1 DD 28 D 32 31 30 29 28 27 26 25 NC 2 27 VSS NC S16 1 24 S8 3 26 S8 S15 2 23 S7 S16 4 25 S7 S14 3 22 S6 ADG1406 S15 5 24 S6 S13 4 21 S5 S12 5 TOP VIEW 20 S4 S14 (Not to Scale) 6 23 S5 ADG1406 S11 6 19 S3 S13 7 22 S4 S10 7 18 S2 TOP VIEW S9 8 17 S1 S12 8 (Not to Scale) 21 S3 S11 9 9 20 S2 10 11 12 13 14 15 16 3 2 1 0 S10 D C C N 10 19 S1 N A A N N A A E G S9 11 18 EN 1. NC = NO CONNECT. DO NOT CONNECT GND 12 17 A0 TO THIS PIN.
4 00
2. THE EXPOSED PAD MUST BE TIED TO NC
9-
13 16 A1 THE SUBSTRATE, V
741
SS.
0
A3 14 15 A2
003
NC = NO CONNECT
07419- Figure 3. ADG1406 TSSOP Pin Configuration Figure 4. ADG1406 LFCSP Pin Configuration
Table 9. ADG1406 Pi n Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description
1 31 VDD Most Positive Power Supply Potential. 2, 3, 13 12, 13, 26, 27, NC No Connect. 28, 30, 32 4 1 S16 Source Terminal 16. This pin can be an input or an output. 5 2 S15 Source Terminal 15. This pin can be an input or an output. 6 3 S14 Source Terminal 14. This pin can be an input or an output. 7 4 S13 Source Terminal 13. This pin can be an input or an output. 8 5 S12 Source Terminal 12. This pin can be an input or an output. 9 6 S11 Source Terminal 11. This pin can be an input or an output. 10 7 S10 Source Terminal 10. This pin can be an input or an output. 11 8 S9 Source Terminal 9. This pin can be an input or an output. 12 9 GND Ground (0 V) Reference. 14 10 A3 Logic Control Input. 15 11 A2 Logic Control Input. 16 14 A1 Logic Control Input. 17 15 A0 Logic Control Input. 18 16 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 17 S1 Source Terminal 1. This pin can be an input or an output. 20 18 S2 Source Terminal 2. This pin can be an input or an output. 21 19 S3 Source Terminal 3. This pin can be an input or an output. 22 20 S4 Source Terminal 4. This pin can be an input or an output. 23 21 S5 Source Terminal 5. This pin can be an input or an output. 24 22 S6 Source Terminal 6. This pin can be an input or an output. 25 23 S7 Source Terminal 7. This pin can be an input or an output. 26 24 S8 Source Terminal 8. This pin can be an input or an output. 27 25 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 28 29 D Drain Terminal. This pin can be an input or an output. Not applicable 0 EPAD Exposed Pad. The exposed pad must be tied to the substrate, VSS. Rev. C | Page 9 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY 12 V SINGLE SUPPLY ±5 V DUAL SUPPLY CONTINUOUS CURRENT PER CHANNEL ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE