Datasheet NC7SV57, NC7SV58 (ON Semiconductor) - 8
| Hersteller | ON Semiconductor |
| Beschreibung | TinyLogic ULP-A Universal Configurable 2-Input Logic Gates |
| Seiten / Seite | 13 / 8 — NC7SV57, NC7SV58. Test. Switch Position. Figure 12. Test Circuit. VCC, V. … |
| Revision | 3 |
| Dateiformat / Größe | PDF / 380 Kb |
| Dokumentensprache | Englisch |
NC7SV57, NC7SV58. Test. Switch Position. Figure 12. Test Circuit. VCC, V. Vmi, V. Vmo, V. VY, V. Figure 13. Switching Waveforms
Modelllinie für dieses Datenblatt
Textversion des Dokuments
NC7SV57, NC7SV58
OPEN
Test Switch Position
2 x VCC GND tPLH / tPHL Open tPLZ / tPZL 2 x VCC R1 INPUT tPHZ / tPZH GND DUT OUTPUT RT RL CL* CL includes probe and jig capacitance RT is ZOUT of pulse generator (typically 50 W) f = 1 MHz
Figure 12. Test Circuit
t V r = 3 ns tf = 3 ns CC V 90% 90% CC INPUT Vmi Vmi INPUT Vmi Vmi 10% 10% GND GND tPZL tPLZ tPHL tPLH ~VCC VOH OUTPUT V OUTPUT V mo mo Vmo VOL + VY V V OL OL t t PZH tPHZ PLH tPHL V V OH OH VOH − VY OUTPUT Vmo Vmo OUTPUT Vmo VOL ~0 V
VCC, V Vmi, V Vmo, V VY, V
0.9 VCC / 2 VCC / 2 0.1 1.1 to 1.3 VCC / 2 VCC / 2 0.1 1.4 to 1.6 VCC / 2 VCC / 2 0.1 1.65 to 1.95 VCC / 2 VCC / 2 0.15 2.3 to 2.7 VCC / 2 VCC / 2 0.15 3.0 to 3.6 1.5 1.5 0.3
Figure 13. Switching Waveforms www.onsemi.com 8
OPEN
Test Switch Position
2 x VCC GND tPLH / tPHL Open tPLZ / tPZL 2 x VCC R1 INPUT tPHZ / tPZH GND DUT OUTPUT RT RL CL* CL includes probe and jig capacitance RT is ZOUT of pulse generator (typically 50 W) f = 1 MHz
Figure 12. Test Circuit
t V r = 3 ns tf = 3 ns CC V 90% 90% CC INPUT Vmi Vmi INPUT Vmi Vmi 10% 10% GND GND tPZL tPLZ tPHL tPLH ~VCC VOH OUTPUT V OUTPUT V mo mo Vmo VOL + VY V V OL OL t t PZH tPHZ PLH tPHL V V OH OH VOH − VY OUTPUT Vmo Vmo OUTPUT Vmo VOL ~0 V
VCC, V Vmi, V Vmo, V VY, V
0.9 VCC / 2 VCC / 2 0.1 1.1 to 1.3 VCC / 2 VCC / 2 0.1 1.4 to 1.6 VCC / 2 VCC / 2 0.1 1.65 to 1.95 VCC / 2 VCC / 2 0.15 2.3 to 2.7 VCC / 2 VCC / 2 0.15 3.0 to 3.6 1.5 1.5 0.3
Figure 13. Switching Waveforms www.onsemi.com 8