Datasheet AD8555 (Analog Devices) - 9

Data Sheet AD8555 DD DD V VSS VSS A DV A D 16 15 14 13 NC 1 12 VOUT FILT/DIGOUT 2 11 NC AD8555 TOP VIEW NC 3 10 VCLAMP DIGIN 4 9 NC 5 6 7 8 S NC EG NC VN VPO NOTES 1. NC = NO CONNECT.
050
2. THE EXPOSED PAD MUST BE CONNECTED TO DVSS (PIN 13).
04598- Figure 3. 16-Lead LFCSP (Not Drawn to Scale)
Table 6. 16-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description
0 EPAD Exposed Pad. The exposed pad must be connected to DVSS (Pin 13). 1, 3, 5, 7, 9, 11 NC Do Not Connect. 2 FILTDIGOUT Unbuffered Amplifier Output In Series with a Resistor RF. Adding a capacitor between FILT and VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a digital output. 4 DIGIN Digital Input. 6 VNEG Negative Amplifier Input (Inverting Input). 8 VPOS Positive Amplifier Input (Noninverting Input). 10 VCLAMP Set Clamp Voltage at Output. 12 VOUT Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a buffered digital output. 13, 14 DVSS, AVSS Negative Supply Voltage. 15, 16 DVDD, Positive Supply Voltage. AVDD Rev. B | Page 9 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION GAIN VALUES OPEN WIRE FAULT DETECTION SHORTED WIRE FAULT DETECTION FLOATING VPOS, VNEG, OR VCLAMP FAULT DETECTION DEVICE PROGRAMMING Digital Interface Initial State Simulation Mode Programming Mode Parity Error Detection Read Mode Sense Current Suggested Programming Procedure Suggested Algorithm to Determine Optimal Gain and Offset Codes FILTERING FUNCTION DRIVING CAPACITIVE LOADS RF INTERFERENCE SINGLE-SUPPLY DATA ACQUISITION SYSTEM USING THE AD8555 WITH CAPACITIVE SENSORS OUTLINE DIMENSIONS ORDERING GUIDE