Datasheet nPM1100 (Nordic Semiconductor) - 10

HerstellerNordic Semiconductor
BeschreibungIntegrated Power Management IC (PMIC) with a linear-mode lithium-ion/lithium-polymer battery charger in a compact 2.1x2.1 mm WLCSP package
Seiten / Seite58 / 10 — VOUTSET1. VBUS. VBAT. VSYS. VOUTB. SHPACT. SHPHLD. SHIPACT. Note:
Dateiformat / GrößePDF / 2.9 Mb
DokumentenspracheEnglisch

VOUTSET1. VBUS. VBAT. VSYS. VOUTB. SHPACT. SHPHLD. SHIPACT. Note:

VOUTSET1 VBUS VBAT VSYS VOUTB SHPACT SHPHLD SHIPACT Note:

Modelllinie für dieses Datenblatt

Textversion des Dokuments

link to page 28 link to page 10 link to page 11 link to page 16 link to page 24 link to page 24 link to page 16 link to page 24 link to page 23 link to page 12 link to page 12 link to page 12 link to page 12 link to page 12 Product overview
VOUTSET1
) for different application circuit requirements. BUCK is supplied by VINT (from SYSREG or the battery). See BUCK — Buck regulator on page 28 for more information and electrical parameters. The device also features Ship mode, the lowest quiescent current state. It disconnects the battery from the system and reduces the quiescent current of the device to extend battery life when products are in storage. See Using Ship mode on page 10 and Charging and Error LED drivers on page 11 for more information. 3.3 Power-on reset (POR) and brownout reset (BOR) When one of the following conditions are met, a power-on reset (POR) occurs. •
VBUS
voltage rises above VBUSPOR •
VBAT
voltage rises above VBATPOR VBATPOR has a minimum and maximum range. To ensure the device exits reset, the voltage should be above the maximum of the parameter. When both of the following conditions are met, a brownout reset (BOR) occurs. •
VBUS
voltage falls below VBUSBOR •
VBAT
voltage falls below VBATBOR BOR may occur if both supply voltages are below the maximum of the parameter range. BOR occurs if both supply voltages are below the minimum of the parameter range. The device is held in reset, or System OFF, when both supply voltages
VBAT
and
VBUS
are below minimum thresholds. 3.4 DPPM — Dynamic power-path management Dynamic power-path management (DPPM) is a feature that regulates internal voltage (VINT) as system load (ISYS) changes to maintain supply to the application circuit (supplied by the
VSYS
and
VOUTB
pins). CHARGER applies DPPM during charging, after charging completes, or when the
VBUS
pin is disconnected, to dynamically control current in and out of the battery. See DPPM — Dynamic power-path management on page 23. 3.5 Using Ship mode Ship mode isolates the battery, reducing quiescent current. To enter Ship mode,
SHPACT
must be set high for a minimum period of tactiveToShip when
VBUS
is disconnected and
SHPHLD
held high (VIH).
SHPACT
has an internal pull-down resistor.
SHIPACT
can be connected to a microcontroller GPIO (using logic levels in the range VIL and VIH) or to a PCB test pin for activation at the end of production.
Note: VBUS
must be discharged to below minimum level VBUSMIN which may require waiting for any capacitive discharge before activating
SHPACT
. There are two ways to exit Ship mode. Either connect the USB (
VBUS
) or set
SHPHLD
low for a minimum period of tshipToActive. The battery supply (
VBAT
) is used to hold
SHPHLD
high through a weak pull-up resistor when Ship mode is enabled. A circuit to pull
SHPHLD
down is optional (see the Button switch shown in the following figure). If no pull-down circuit is present, Ship mode is exited when
VBUS
is connected. 4445_367 v1.0 10 Document Outline Contents nPM1100 Feature list Revision history About this document 2.1 Document status 2.2 Core component chapters Product overview 3.1 Block diagram 3.1.1 In circuit configurations 3.2 System description 3.3 Power-on reset (POR) and brownout reset (BOR) 3.4 DPPM — Dynamic power-path management 3.5 Using Ship mode 3.6 Thermal protection 3.7 Battery considerations 3.8 Charging and Error LED drivers 3.9 System electrical parameters 3.10 System efficiency Absolute maximum ratings Recommended operating conditions 5.1 Dissipation ratings 5.2 WLCSP light sensitivity Core components 6.1 SYSREG — System regulator 6.1.1 USB port detection and VBUS current limiting 6.1.2 SYSREG resistance and output voltage 6.1.3 VBUS overvoltage and undervoltage protection 6.1.4 VBUS disconnect 6.1.5 Electrical parameters 6.1.6 Electrical characteristics 6.2 CHARGER — Battery charger 6.2.1 Charging cycle 6.2.2 Battery detection and UVLO 6.2.3 Termination voltage (VTERMSET) 6.2.4 Termination and trickle charge current 6.2.5 Charge current limit (ICHG) 6.2.6 Battery thermal protection using NTC thermistor (NTC) 6.2.7 Charger thermal regulation 6.2.8 Charger error conditions 6.2.9 Charging indication (CHG) and charging error indication (ERR) 6.2.10 DPPM — Dynamic power-path management 6.2.11 Electrical parameters 6.2.12 Electrical characteristics 6.3 BUCK — Buck regulator 6.3.1 Output voltage selection (VOUTBSET0, VOUTBSET1) 6.3.2 BUCK mode selection (MODE) 6.3.3 Component selection 6.3.4 Electrical parameters 6.3.5 Electrical characteristics Application 7.1 Schematic 7.2 Supplying from BUCK 7.3 USB port negotiation 7.4 CHG and ERR 7.5 Termination voltage and current 7.6 NTC configuration 7.7 Ship mode 7.8 Battery monitoring and low battery indication Hardware and layout 8.1 Ball assignments 8.2 Mechanical specifications 8.2.1 WLCSP 2.075x2.075 mm package 8.3 Reference circuitry 8.3.1 Configuration 1 8.3.2 Configuration 2 8.3.3 Configuration 3 8.3.4 PCB guidelines 8.3.5 PCB layout example Ordering information 9.1 IC marking 9.2 Box labels 9.3 Order code 9.4 Code ranges and values 9.5 Product options Legal notices