Datasheet LM73100 (Texas Instruments) - 50

HerstellerTexas Instruments
Beschreibung2.7 -23 V, 5.5 A Integrated Ideal Diode with Input Reverse Polarity and Overvoltage Protection
Seiten / Seite52 / 50 — EXAMPLE BOARD LAYOUT. RPW0010A. VQFN-HR - 1 mm max height. www.ti.com
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DokumentenspracheEnglisch

EXAMPLE BOARD LAYOUT. RPW0010A. VQFN-HR - 1 mm max height. www.ti.com

EXAMPLE BOARD LAYOUT RPW0010A VQFN-HR - 1 mm max height www.ti.com

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EXAMPLE BOARD LAYOUT RPW0010A VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD (1.8) (1.45) 4X (0.475) 2X (0.25) 1 10 4X (0.25) 4X PKG 2X (0.225) 2X (1.75) (2.4) 4X (0.475) 4X (0.3) 7 4 4X (0.65) (R0.05) TYP 5 6 2X (0.3) 4X (0.25) PKG 8X (0.6) LAND PATTERN EXAMPLE SCALE: 30X SOLDER MASK 0.05 MAX 0.05 MIN OPENING ALL AROUND ALL AROUND METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL NON- SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE 4225183/A 08/2019 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Timing Requirements 6.7 Switching Characteristics 6.8 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Reverse Polarity Protection 7.3.2 Undervoltage Protection (UVLO & UVP) 7.3.3 Overvoltage Lockout (OVLO) 7.3.4 Inrush Current control and Fast-trip 7.3.4.1 Slew Rate (dVdt) and Inrush Current Control 7.3.4.2 Fast-Trip During Steady State 7.3.5 Analog Load Current Monitor Output 7.3.6 Reverse Current Protection 7.3.7 Overtemperature Protection (OTP) 7.3.8 Fault Response 7.3.9 Power Good Indication (PG) 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Single Device, Self-Controlled 8.2.1 Typical Application 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds 8.2.1.2.2 Setting Output Voltage Rise Time (tR) 8.2.1.2.3 Setting Power Good Assertion Threshold 8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range 8.2.1.3 Application Curves 8.3 Active ORing 8.4 Priority Power MUXing 8.5 USB PD Port Protection 8.6 Parallel Operation 9 Power Supply Recommendations 9.1 Transient Protection 10 Layout 10.1 Layout Guidelines 10.2 Layout Example 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 Related Documentation 11.2 Receiving Notification of Documentation Updates 11.3 Support Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information