Datasheet STK14CA8C (Infineon) - 4

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STK14CA8C Device Operation
Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical The STK14CA8C nvSRAM is made up of two functional Characteristics on page 7 for the size of VCAP. The voltage on components paired in the same physical cell. They are an SRAM the VCAP pin is driven to VCC by a regulator on the chip. Place a memory cell and a nonvolatile QuantumTrap cell. The SRAM pull-up on WE to hold it inactive during power-up. This pull-up is memory cell operates as a standard fast static RAM. Data in the only effective if the WE signal is tristate during power-up. Many SRAM is transferred to the nonvolatile cell (the STORE MPUs tristate their controls on power-up. This must be verified operation), or from the nonvolatile cell to the SRAM (the RECALL when using the pull-up. When the nvSRAM comes out of operation). Using this unique architecture, all cells are stored and power-on-RECALL, the MPU must be active or the WE held recalled in parallel. During the STORE and RECALL operations, inactive until the MPU comes out of reset. SRAM read and write operations are inhibited. The STK14CA8C supports infinite reads and writes similar to a typical SRAM. In To reduce unnecessary nonvolatile stores, AutoStore and addition, it provides infinite RECALL operations from the Hardware STORE operations are ignored unless at least one nonvolatile cells and up to 1 million STORE operations. Refer to write operation has taken place since the most recent STORE or the Truth Table For SRAM Operations on page 16 for a complete RECALL cycle. Software initiated STORE cycles are performed description of read and write modes. regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore
SRAM Read
cycle is in progress. The STK14CA8C performs a read cycle when CE and OE are
Figure 2. AutoStore Mode
LOW and WE and HSB are HIGH. The address specified on pins
VCC
A0-16 determines which of the 131,072 data bytes each are accessed. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at t
0.1 uF
ACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without
VCC
the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought
10 kOhm
HIGH, or WE or HSB is brought LOW.
SRAM Write WE VCAP
A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the
VCAP
write cycle and must remain stable until CE or WE goes HIGH at
VSS
the end of the cycle. The data on the common I/O pins DQ0–7 are written into the memory if the data is valid tSD before the end of a WE-controlled write or before the end of a CE-controlled write. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal
Hardware STORE Operation
circuitry turns off the output buffers tHZWE after WE goes LOW. The STK14CA8C provides the HSB pin to control and
AutoStore Operation
acknowledge the STORE operations. Use the HSB pin to request a Hardware STORE cycle. When the HSB pin is driven The STK14CA8C stores data to the nvSRAM using one of the LOW, the STK14CA8C conditionally initiates a STORE operation following three storage operations: Hardware STORE activated after t by HSB; Software STORE activated by an address sequence; DELAY. An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle. AutoStore on device power-down. The AutoStore operation is a The HSB pin also acts as an open drain driver (internal 100 k unique feature of QuantumTrap technology and is enabled by weak pull-up resistor) that is internally driven LOW to indicate a default on the STK14CA8C. busy condition when the STORE (initiated by any means) is in During a normal operation, the device draws current from VCC to progress. charge a capacitor connected to the VCAP pin. This stored
Note
After each Hardware and Software STORE operation HSB charge is used by the chip to perform a single STORE operation. is driven HIGH for a short time (t If the voltage on the V HHHD) with standard output high CC pin drops below VSWITCH, the part current and then remains HIGH by internal 100 k pull-up automatically disconnects the VCAP pin from VCC. A STORE resistor. operation is initiated with power provided by the VCAP capacitor. SRAM write operations that are in progress when HSB is driven
Note
If the capacitor is not connected to VCAP pin, AutoStore LOW by any means are given time (t must be disabled using the soft sequence specified in Preventing DELAY) to complete before the STORE operation is initiated. However, any SRAM write AutoStore on page 5. In case AutoStore is enabled without a cycles requested after HSB goes LOW are inhibited until HSB capacitor on VCAP pin, the device attempts an AutoStore returns HIGH. In case the write latch is not set, HSB is not driven operation without sufficient charge to complete the Store. This LOW by the STK14CA8C. But any SRAM read and write cycles corrupts the data stored in nvSRAM. are inhibited until HSB is returned HIGH by MPU or other external source. Document Number: 002-23970 Rev. *A Page 4 of 21 Document Outline 1-Mbit (128K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support