Datasheet ADP5054 (Analog Devices) - 28

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ADP5054 Data Sheet PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Optimal circuit board layout is essential to obtain the best Use a ground plane with several vias connecting to the performance from the ADP5054 (see Figure 43). Poor layout component side ground to further reduce noise can affect the regulation and stability of the device, as well as interference on sensitive circuit nodes. the EMI and electromagnetic compatibility (EMC) performance. Place the decoupling capacitors close to the VREG and For a optimal PCB layout, refer to the following guidelines: VDD pins. Place the input capacitor, inductor, MOSFET, output Place the frequency setting resistor close to the RT pin. capacitor, and bootstrap capacitor close to the IC. Place the feedback resistor divider close to the FBx pin. In Use short, thick traces to connect the input capacitors addition, keep the FBx traces away from the high current to the PVINx pins, and use a dedicated power ground to traces and the switch node to avoid noise pickup. connect the input and output capacitor grounds to Use 0402 or 0603 size resistors and capacitors to achieve minimize the connection length. the smallest possible footprint solution on boards where Use several high current vias, if required, to connect space is limited. PVINx, PGNDx, or SWx to other power planes.
V
Use short, thick traces to connect the inductors to the
IN PVINx BSTx
SWx pins and the output capacitors.
VOUT SWx
Ensure that the high current loop traces are as short and wide as possible. The high current path is shown in Figure 42.
DLx
Maximize the amount of ground metal for the exposed
ENx FBx
pad, and use as many vias as possible on the component
GND
022 side to improve thermal dissipation. 17- 126 Figure 42. Typical Circuit with High Current Traces Shown in Blue
VOUT1 R 0402 R 0402 R 0402 R 0402 COUTx - 47 µF COUTx - 47 µF 6.3V/X5R 6.3V/X5R L1 0805 0805 CINx - 10 µF 402 402 C0 R0 402 0402 25 V/XR 5 R C0 5 5 0805 VOUT3 5 5 R R F /X F 5 /X 02 02 402 1µ V 1µ V 3 04 3 04 R0 6. 6. R R µF µF 0 /XRX 06 /XRX 00 V 000 V 12 1206 5 R µF 10 3 1206 10 3 /X 1 0. 3V 0402 6. 6. 6. COUT CO x UT - 47 47 µF µF 6.3V/X5R 0805 48 47 46 45 44 43 42 41 40 39 38 37 EN 3 COMP 3 FB 3 VREG SYNC / VDD RT FB 1 COMP 1 EN 1 PVIN 1 PVIN 1 MOD MO E 1 BST 3 PVIN P 1 36 L3 2 PGND 3 SW 1 35 2 G G2 2 D D2 3 PGND 3 SW 1 34 CIN CI x - 10 10 µF µF 4 25 V/X5R SW 3 SW 1 33 25 V/X5R 5 33 F R µF 2 1µ /X 1 V 0240 0805 0. 3 04 6. 05 4020204 5 SW 3 BS B T 1 32 R0R 2 S S2 2 D D2 DUAL FET 6 PVIN 3 31 DL 1 ADP5054 BSC072N03LD 7 PVIN 4 30 PGND 1 G 1 OR Si4204DY 8 SW 4 DL 2 29 1 D1 D1 CINx CINx - 10 10 µF 25 25 V/ V/X5 X5R 9 SW 4 BST 2 28 0805 5 40204 F R R0 µF R /XR 2 1µ /X 10 SW 2 27 .1 V 0.0 33V 040 PGND 4 27 66. 1 S S1 1 D D1 11 26 PGND 4 SW 2 12 SW 2 25 BST 4 PWRGD CFG 12 FB 2 COMP 2 EN 2 CFG 34 EN 4 COMP 4 FB 4 PVIN 2 PVIN 2 PVIN 2 L4 13 14 15 16 17 18 19 20 21 22 23 24 COUT CO x UT - 47 47 µF 6.3V/X5R 5 5 5 F R 0805 µF 05 1µ /X .1 V 0.0 33V 0402 R R 66. µF 6 µF 6 0 /X /X V 0 V 2 2 10 2 .3 1 10 .3 1 040 040 10 3 120 10 3 120 040 0402 R C 6 6 C R 6. 6. CINx - 10 µF L2 25 V/XR 5 VOUT4 0805 R 0402 R 0402 CO C U OUTx T - 47 µF COU CO Tx Tx - 47 µF 6. 6 3V 3V/X5R 6. 6.3V/X5R 5R 0805 0805 R 0402 R 0402 VOUT2
3 -04 17 126 Figure 43. Typical PCB Layout for the ADP5054 Rev. G | Page 28 of 31 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGE INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK PULSE SKIP IN MAXIMUM DUTY SHORT-CIRCUIT PROTECTION (SCP) LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUIT FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE