Datasheet AD5560 (Analog Devices) - 65

Data Sheet AD5560 OUTLINE DIMENSIONS 12.20 1.20 0.675 MAX 12.00 SQ 0.75 0.872 5.95 BSC 11.80 0.60 0.45 64 49 49 64 1 48 48 1 1.00 REF SEATING PLANE 10.20 EXPOSED 7.85 10.00 SQ PAD BSC 5.95 9.80 BSC TOP VIEW (PINS DOWN) 1.05 BOTTOM VIEW (PINS UP) 16 33 33 16 1.00 0.20 17 32 32 17 0.95 0.09 7.85 7° 0.27 0.15 VIEW A BSC 3.5° 0.50 0.22 0.05 0.08 0° FOR PROPER CONNECTION OF BSC 0.17 COPLANARITY THE EXPOSED PAD, REFER TO LEAD PITCH THE PIN CONFIGURATION AND -C FUNCTION DESCRIPTIONS 1 1 VIEW A SECTION OF THIS DATA SHEET. 20 ROTATED 90° CCW 19- COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HU 10-
Figure 64. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-64-3) Dimensions shown in millimeters
8.10 8.00 SQ 7.90 5.720 REF 0.40 REF A1 BALL A1 BALL (DIE OFFSET) CORNER CORNER 9 8 7 6 5 4 3 2 1 A B C 6.40 6.865 REF D BSC SQ E F G 0.80 BSC H J TOP VIEW 0.80 BOTTOM VIEW REF DETAIL A * 0.81 1.20 DETAIL A 0.76 1.08 0.36 0.71 1.00 REF 0.39 0.34 0.50 0.29 COPLANARITY 0.45 0.12 SEATING 0.40 PLANE BALL DIAMETER B * 2012- COMPLIANT TO JEDEC STANDARDS MO-225 WITH 19- EXCEPTION TO PACKAGE HEIGHT. 04-
Figure 65. 72-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-72-2) Dimensions shown in millimeters Rev. E | Page 65 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE