Datasheet AD5560 (Analog Devices) - 21

Data Sheet AD5560 0.0500 0.0500 HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D AV LOW: AV DD = +16.25V DD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB AV NOM: AV SS = –16.25V DD/AVSS = ±16.25V, OFFSET DAC = 0x8000 0.0375 0.0375 V VREF = 5V REF = 5V ±25mA RANGE OFFSET DAC = 0x8000 0.0250 0.0250 MI GAIN = 20 MEASOUT GAIN = 0.2 25µA RANGE NOMINAL SUPPLIES %) 0.0125 %) 0.0125 ( ( Y Y T LOW SUPPLIES T 0 0 ARI ARI INE INE L –0.0125 L –0.0125 –0.0250 –0.0250 2.5mA –0.0375 –0.0375 25mA RANGE HIGH SUPPLIES –0.0500 –0.0500
037
0 10,000 20,000 30,000 40,000 50,000 60,000 70,000
040
0 10,000 20,000 30,000 40,000 50,000 60,000 CODE
07779-
CODE
07779- Figure 14. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2, Figure 17. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 0.2, MI Gain = 20) MI Gain = 20)
0.100 1.5 HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D LOW : AV T DD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB J = 25°C NOM : AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000 0.075 1.0 VREF = 5V ±25mA RANGE 0.5 0.050 A) HIGH SUPPLIES n ( 0 %) 0.025 NT ( Y –0.5 EXTFORCE1A T EXTFORCE2B 0 ARI FORCE CURRE E –1.0 EXTFORCE1B INE EXTMEASIH1 L –0.025 NOMINAL SUPPLIES –1.5 SENSE AKAG EXTFORCE1C E –0.050 L EXTMEASIH2 LOW SUPPLIES –2.0 SYS_FORCE EXTFORCE2A –0.075 –2.5 EXTMEASIL SYS_SENSE COMBINED LEAKAGE –0.100 –3.0
038
0 10,000 20,000 30,000 40,000 50,000 60,000 70,000
030
–10 5 0 5 10 CODE
07779-
STRESS VOLTAGE (V)
07779- Figure 15. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2, Figure 18. Leakage Current vs. Stress Voltage (Force and Combined Leakage) MI Gain = 10)
0.0100 7 AVDD = +16.25V V AV STRESS = 9V SS = –16.25V 0.0075 VREF = 5V 6 OFFSET DAC = 0x8000 25µA RANGE 0.0050 MI GAIN = 20 MEASOUT GAIN = 1 A) 5 n ( EXTFORCE1A %) 0.0025 NT EXTFORCE2B ( Y 4 FORCE T EXTFORCE1B 0 EXTMEASIH1 ARI CURRE SENSE E 3 INE EXTFORCE1C L –0.0025 2.5mA EXTMEASIH2 AKAG SYS_FORCE E 2 –0.0050 EXTFORCE2A L EXTMEASIL SYS_SENSE –0.0075 25mA RANGE 1 COMBINED LEAKAGE –0.0100 0
039
0 10,000 20,000 30,000 40,000 50,000 60,000
031
25 35 45 55 65 75 85 95 CODE
07779-
TEMPERATURE (°C)
07779- Figure 16. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 1, Figure 19. Leakage Current vs. Temperature (Force and Combined Leakage), MI Gain = 20) VSTRESS = 9 V Rev. E | Page 21 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE