Datasheet AD8324 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | 3.3 V DOCSIS 2.0 Upstream Cable Line Driver |
| Seiten / Seite | 16 / 2 — AD8324. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 5/16—Rev. B to … |
| Revision | C |
| Dateiformat / Größe | PDF / 427 Kb |
| Dokumentensprache | Englisch |
AD8324. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 5/16—Rev. B to Rev. C. 7/13—Rev. A to Rev. B. 7/05—Rev. 0 to Rev. A
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AD8324 Data Sheet TABLE OF CONTENTS
Features .. 1 Gain Programming for the AD8324 .. 12 Applications ... 1 Input Bias, Impedance, and Termination.. 12 Functional Block Diagram .. 1 Output Bias, Impedance, and Termination .. 12 General Description ... 1 Power Supply ... 13 Revision History ... 2 Signal Integrity Layout Considerations ... 13 Specifications ... 3 Initial Power-Up ... 13 Logic Inputs (TTL-/CMOS-Compatible Logic) ... 4 RAMP Pin and BYP Pin Features .. 13 Timing Requirements .. 5 Power Saving Features ... 14 Absolute Maximum Ratings .. 6 Distortion, Adjacent Channel Power, and DOCSIS .. 14 Thermal Resistance .. 6 Utilizing Diplex Filters ... 14 ESD Caution .. 6 Noise and DOCSIS ... 14 Pin Configuration and Function Descriptions ... 7 Differential Signal Source.. 15 Typical Performance Characteristics ... 8 Differential Signal from Single-Ended Source ... 15 Test Circuit .. 11 Single-Ended Source .. 15 Applications Information .. 12 Outline Dimensions ... 16 General Applications .. 12 Ordering Guide .. 16 Circuit Description... 12
REVISION HISTORY 5/16—Rev. B to Rev. C
Controlling Gain/Attenuation of the AD8324 Section, Change CP-20-1 to CP-20-6 .. Universal Figure 28, Transmit Enable and Sleep Mode Section, and Changes to Figure 5, Figure 6, and Table 6 ... 7 Memory Functions Section ... 14 Changes to Figure 23 .. 13 Changes to Distortion, Adjacent Channel Power, and DOCSIS Updated Outline Dimensions ... 16 Section and Noise and DOCSIS Section ... 14 Changes to Ordering Guide .. 16 Deleted Figure 29 .. 15
Changes to Differential Signal from Single-Ended Source
7/13—Rev. A to Rev. B
Section, Single-Ended Source Section, Figure 26, and Table 8 15 Changes to General Description Section .. 1 Updated Outline Dimensions ... 16 Changes to Table 6 .. 7 Changes to Ordering Guide .. 16 Added Test Circuits Section .. 11 Changed Applications Section to Applications Information
7/05—Rev. 0 to Rev. A
Section .. 12 Updated Absolute Maximum Ratings Page ... 5 Changes to Output Bias, Impedance, and Termination Section . .. 12 Updated Outline Dimensions ... 16 Deleted Evaluation Board Features and Operation Section ... 13 Changes to Ordering Guide .. 16 Deleted Overshoot on PC Printer Ports Section, Installing Visual Basic Control Software Section, Running AD8324
10/03—Revision 0: Initial Version
Software Section, Figure 27; Renumbered Sequential y, Rev. C | Page 2 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE
AD8324 Data Sheet TABLE OF CONTENTS
Features .. 1 Gain Programming for the AD8324 .. 12 Applications ... 1 Input Bias, Impedance, and Termination.. 12 Functional Block Diagram .. 1 Output Bias, Impedance, and Termination .. 12 General Description ... 1 Power Supply ... 13 Revision History ... 2 Signal Integrity Layout Considerations ... 13 Specifications ... 3 Initial Power-Up ... 13 Logic Inputs (TTL-/CMOS-Compatible Logic) ... 4 RAMP Pin and BYP Pin Features .. 13 Timing Requirements .. 5 Power Saving Features ... 14 Absolute Maximum Ratings .. 6 Distortion, Adjacent Channel Power, and DOCSIS .. 14 Thermal Resistance .. 6 Utilizing Diplex Filters ... 14 ESD Caution .. 6 Noise and DOCSIS ... 14 Pin Configuration and Function Descriptions ... 7 Differential Signal Source.. 15 Typical Performance Characteristics ... 8 Differential Signal from Single-Ended Source ... 15 Test Circuit .. 11 Single-Ended Source .. 15 Applications Information .. 12 Outline Dimensions ... 16 General Applications .. 12 Ordering Guide .. 16 Circuit Description... 12
REVISION HISTORY 5/16—Rev. B to Rev. C
Controlling Gain/Attenuation of the AD8324 Section, Change CP-20-1 to CP-20-6 .. Universal Figure 28, Transmit Enable and Sleep Mode Section, and Changes to Figure 5, Figure 6, and Table 6 ... 7 Memory Functions Section ... 14 Changes to Figure 23 .. 13 Changes to Distortion, Adjacent Channel Power, and DOCSIS Updated Outline Dimensions ... 16 Section and Noise and DOCSIS Section ... 14 Changes to Ordering Guide .. 16 Deleted Figure 29 .. 15
Changes to Differential Signal from Single-Ended Source
7/13—Rev. A to Rev. B
Section, Single-Ended Source Section, Figure 26, and Table 8 15 Changes to General Description Section .. 1 Updated Outline Dimensions ... 16 Changes to Table 6 .. 7 Changes to Ordering Guide .. 16 Added Test Circuits Section .. 11 Changed Applications Section to Applications Information
7/05—Rev. 0 to Rev. A
Section .. 12 Updated Absolute Maximum Ratings Page ... 5 Changes to Output Bias, Impedance, and Termination Section . .. 12 Updated Outline Dimensions ... 16 Deleted Evaluation Board Features and Operation Section ... 13 Changes to Ordering Guide .. 16 Deleted Overshoot on PC Printer Ports Section, Installing Visual Basic Control Software Section, Running AD8324
10/03—Revision 0: Initial Version
Software Section, Figure 27; Renumbered Sequential y, Rev. C | Page 2 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE