Datasheet HMC754S8GE (Analog Devices)

HMC754S8GE
v01.1119
GaAs HBT HIGH LINEARITY PUSH-PULL AMPLIFIER, 75 Ohm, DC - 1 GHz Typical Applications Features
8 The HMC754S8GE is ideal for: Output IP2: +78 dBm • CATV / Broadband Infrastructure High Gain: 14.5 dB • Test & Measurement Equipment High Output IP3: +38 dBm T • Line Amps and Fiber Nodes 75 Ohm Impedance M • Customer Premise Equipment Single Positive Supply: +5V Robust 1000V ESD, Class 1C K - S SOIC-8 SMT Package C
Functional Diagram General Description
LO The HMC754S8GE is a GaAs/InGaP HBT Dual Channel Gain Block MMIC SMT amplifier covering DC to 1 GHz. This versatile product contains two IN B gain blocks, packaged in a single 8 lead plastic A SOIC-8, for use with both amplifiers combined in push-pull configuration using external baluns to cancel out second order non-linearities and improve IP2 performance. In this configuration, the HMC754S8GE R & G offers high gain, very low distortion & simple external E matching. This high linearity amplifier consumes only IV 160mA from a single positive supply. R S - D
Electrical Specifications, T = +25° C, Vcc1 = Vcc2 = 5V, Zo = 75 Ohm [1] A
R Parameter Min. Typ. Max. Units IE 0.05 - 0.5 GHz 13.5 14.7 dB Gain 0.5 - 0.87 GHz 12.7 14.2 dB 0.87 - 1.0 GHz 12.1 13.4 dB LIF P Gain Variation Over Temperature 0.05 - 0.87 GHz 0.008 dB/ °C 0.05 - 0.5 GHz 17 dB M Input Return Loss 0.5 - 0.87 GHz 10 dB A 0.05 - 0.5 GHz 10 dB Output Return Loss 0.5 - 0.87 GHz 20 dB Reverse Isolation 0.05 - 0.87 GHz 23 dB Output Power for 1 dB Compression (P1dB) 0.05 - 0.87 GHz 19.5 21 dBm Output Third Order Intercept Point (IP3) 0.05 - 0.87 GHz 38 dBm (Pout= 0 dBm per tone, 1 MHz spacing) Output Second Order Intercept Point (IP2) 0.05 - 0.5 GHz 78 dBm Composite Second Order (CSO) [2] 0.05 - 0.87 GHz -81 dBc Composite Triple Beat (CTB) [2] 0.05 - 0.87 GHz -75 dBc Cross Modulation (XMOD) [2] 0.05 - 0.87 GHz -67 dBc 0.05 - 0.5 GHz 5.5 dB Noise Figure 0.05 - 0.87 GHz 6.5 dB Supply Current (Icc1 + Icc2) 145 160 175 mA [1] Data taken with dual amplifiers combined in push-pull (default) configuration [2] Input level +15 dBmV, 133 channels - with analog modulation I F nf o or r p mati roic n e fu , d rnis e h leiv d e b ry y , a Analn o d t g D o p evic leac s i e o s bel rid ev e e rs d t : A o b n e a a lco c g D urat e e a v n ic d re elsi, I abl n e c . H , O owe n vee T r, n e o chn F o o lo r p g ri y W ce a , d y el, P ive.O ry . B , anox 9 d t 10 o pl 6 a , N c o e orrw de o r o s d, M : Anal A 0 o 2 g D 0 e 6 vi 2 c - e 9 s 10 , I 6 nc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106
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rights of third parties that may result from its use. SpP e h ci o fic n ate io: 78 ns su1 b - j 3 ec 2 t t 9- o c 4 h 7 an 0 g 0 • O e withourd t n e otir o ce n . N li o ne at www.analog.com license is granted by implication or otherwise under an A y pa p te p n li t o ca r p t atio enn S t rig u ht pp s o o f A rnta: P lo h g D o e n vi e ce : 1 s. -80 P 0 ho -A ne NA : 7 L 81 O -3 G 2 - 9-D4700 • Order online at www.analog.com Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 1-800-ANALOG-D Document Outline Typical Applications Features Functional Diagram General Description Electrical Specifications Typical Performance Characteristics Gain & Return Loss Gain vs. Temperature Input Return Loss vs. Temperature Output Return Loss vs. Temperature Output IP3 vs. Temperature Output IP2 vs. Temperature Noise Figure vs. Temperature P1dB vs. Temperature Reverse Isolation vs. Temperature Output IP2 vs. Output Power CSO / CTB / XMOD @ +15 dBmV input, 133 channels (Analog) Option 1 - Improved Input Return Loss & Gain Flatness (with Lower IP2) Application Gain & Return Loss Output IP2 vs. Frequency Output IP3 vs. Frequency Noise Figure vs. Frequency P1dB vs. Frequency Option 2 - 10 to 100 MHz Application Gain & Return Loss Output IP3 vs. Frequency Noise Figure vs. Frequency P1dB vs. Frequency Absolute Maximum Ratings Outline Drawing Package Information Pin Descriptions Application Circuit for Push-Pull Operation Components for Selected Options Evaluation PCB Option 2 Application List of Materials Option 1 Application List of Materials