Datasheet ADSP-21369 (Analog Devices) - 23

ADSP-21369 Reset Table 13. Reset Parameter Min Max Unit
Timing Requirements t 1 RESET Pulse Width Low 4t ns WRST CK t RESET Setup Before CLKIN Low 8 ns SRST 1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable V and CLKIN (not including start-up time of external clock oscillator). DD
CLKIN tWRST tSRST RESET
Figure 8. Reset
Interrupts
The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts.
Table 14. Interrupts Parameter Min Max Unit
Timing Requirement t IRQx Pulse Width 2 × t + 2 ns IPW PCLK
INTERRUPT INPUTS tIPW
Figure 9. Interrupts Rev. H | Page 23 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide