Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 9

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
The PWM generator is capable of operating in two distinct another serial port to provide TDM support. One SPORT pro- modes while generating center-aligned PWM waveforms: vides two transmit signals while the other SPORT provides the single-update mode or double-update mode. In single-update two receive signals. The frame sync and clock are shared. mode the duty cycle values are programmable only once per Serial ports operate in five modes: PWM period. This results in PWM patterns that are symmetri- cal about the midpoint of the PWM period. In double-update • Standard serial mode mode, a second updating of the PWM registers is implemented • Multichanne l (TDM) mode at the midpoint of the PWM period. In this mode, it is possible • I2S mode to produce asymmetrical PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. • Packed I2S mode PWM signals can be mapped to the external port address lines • Left-justified mode or to the DPI pins.
S/PDIF-Compatible Digital Audio Receiver/Transmitter MediaLB
The S/PDIF receiver/transmitter has no separate DMA chan- The automotive models of the ADSP-2148x processors have an nels. It receives audio data in serial format and converts it MLB interface which allows the processor to function as a into a biphase encoded signal. The serial data input to the media local bus device. It includes support for both 3-pin as well receiver/transmitter can be formatted as left-justified, I2S or as 5-pin media local bus protocols. It supports speeds up to right-justified with word widths of 16, 18, 20, or 24 bits. 1024 FS (49.25 Mbits/sec, FS = 48.1 kHz) and up to 31 logical The serial data, clock, and frame sync inputs to the S/PDIF channels, with up to 124 bytes of data per media local bus frame. receiver/transmitter are routed through the signal routing unit For a list of automotive models, see Automotive Products on (SRU). They can come from a variety of sources, such as the Page 69. SPORTs, external pins, or the precision clock generators (PCGs), and are controlled by the SRU control registers.
Digital Applications Interface (DAI)
The digital applications interface (DAI) allows the connection
Asynchronous Sample Rate Converter (SRC)
of various peripherals to any of the DAI pins (DAI_P20–1). The asynchronous sample rate converter contains four SRC Programs make these connections using the signal routing unit blocks and is the same core as that used in the AD1896 192 kHz (SRU). stereo asynchronous sample rate converter and provides up to The SRU is a matrix routing unit (or group of multiplexers) that 128 dB SNR. The SRC block is used to perform synchronous or enables the peripherals provided by the DAI to be intercon- asynchronous sample rate conversion across independent stereo nected under software control. This allows easy use of the DAI channels, without using internal processor resources. The four associated peripherals for a much wider variety of applications SRC blocks can also be configured to operate together to by using a larger set of algorithms than is possible with noncon- convert multichannel audio data without phase mismatches. figurable signal paths. Finally, the SRC can be used to clean up audio data from jittery clock sources such as the S/PDIF receiver. The DAI includes eight serial ports, four precision clock genera- tors (PCG), a S/PDIF transceiver, four ASRCs, and an input
Input Data Port
data port (IDP). The IDP provides an additional input path to The IDP provides up to eight serial input channels—each with the SHARC core, configurable as either eight channels of serial its own clock, frame sync, and data inputs. The eight channels data, or a single 20-bit wide synchronous parallel data acquisi- are automatically multiplexed into a single 32-bit by eight-deep tion port. Each data channel has its own DMA channel that is FIFO. Data is always formatted as a 64-bit frame and divided independent from the processor’s serial ports. into two 32-bit words. The serial protocol is designed to receive
Serial Ports (SPORTs)
audio channels in I2S, left-justified sample pair, or right-justified mode. The ADSP-2148x features eight synchronous serial ports that provide an inexpensive interface to a wide variety of digital and The IDP also provides a parallel data acquisition port (PDAP), mixed-signal peripheral devices such as Analog Devices’ which can be used for receiving parallel data. The PDAP port AD183x family of audio codecs, ADCs, and DACs. The serial has a clock input and a hold input. The data for the PDAP can ports are made up of two data lines, a clock, and frame sync. The be received from DAI pins or from the external port pins. The data lines can be programmed to either transmit or receive and PDAP supports a maximum of 20-bit data and four different each data line has a dedicated DMA channel. packing modes to receive the incoming data. Serial ports can support up to 16 transmit or 16 receive DMA
Precision Clock Generators
channels of audio data when all eight SPORTs are enabled, or The precision clock generators (PCG) consist of four units, each four full duplex TDM streams of 128 channels per frame. of which generates a pair of signals (clock and frame sync) Serial port data can be automatically transferred to and from derived from a clock input signal. The units, A B, C, and D, are on-chip memory/external memory via dedicated DMA chan- identical in functionality and operate independently of each nels. Each of the serial ports can work in conjunction with other. The two signals generated by each unit are normally used as a serial bit clock/frame sync pair. Rev. H | Page 9 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide