Datasheet ADP1710, ADP1711 (Analog Devices) - 8

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ADP1710/ADP1711 THEORY OF OPERATION
The ADP1710/ADP1711 are low dropout, CMOS linear
ADJUSTABLE OUTPUT VOLTAGE
regulators that use an advanced, proprietary architecture to
(ADP1710 ADJUSTABLE)
provide high power supply rejection ratio (PSRR) and excellent The ADP1710 adjustable version can have its output voltage line and load transient response with just a small 1 μF ceramic set over a 0.8 V to 5.0 V range. The output voltage is set by output capacitor. Both devices operate from a 2.5 V to 5.5 V connecting a resistive voltage divider from OUT to ADJ. The input rail and provide up to 150 mA of output current. output voltage is calculated using the equation Incorporating a novel scaling architecture, ground current is very low when driving light loads. Ground current in shutdown VOUT = 0.8 V (1 + R1/R2) (1) mode is typically 100 nA. where: R1 is the resistor from OUT to ADJ.
IN OUT
R2 is the resistor from ADJ to GND. The maximum bias current into ADJ is 100 nA, so for less than 0.5% error due to the bias current, use values less than
CURRENT LIMIT THERMAL PROTECT
60 kΩ for R2.
+ BYPASS CAPACITOR (ADP1711) SHUTDOWN AND UVLO
The ADP1711 allows for an external bypass capacitor to be
NC/ ADJ/
connected to the internal reference, which reduces output
BYP EN REFERENCE
voltage noise and improves power supply rejection. A low
GND
18 0 leakage capacitor of 1 nF or greater (10 nF is recommended) 0-
NC = NO CONNECT
31 06 must be connected between the BYP and GND pins. Figure 18. Internal Block Diagram
ENABLE FEATURE
Internally, the ADP1710/ADP1711 each consist of a reference, The ADP1710/ADP1711 use the EN pin to enable and disable an error amplifier, a feedback voltage divider, and a PMOS pass the OUT pin under normal operating conditions. As shown in transistor. Output current is delivered via the PMOS pass Figure 19, when a rising voltage on EN crosses the active device, which is controlled by the error amplifier. The error threshold, OUT turns on. When a falling voltage on EN crosses amplifier compares the reference voltage with the feedback the inactive threshold, OUT turns off. voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage.
) V EN /DI
The ADP1710 is available in two versions, one with fixed output
V
voltage options and one with an adjustable output voltage. The
00m 5 2
fixed output voltage option is set internally to one of sixteen
OUT CH2 ( VIN = 5V
values between 0.75 V and 3.3 V, using an internal feedback
VOUT = 1.6V CH1, C
network. The adjustable output voltage can be set to between 0.8
IN = 1µF COUT = 1µF
V and 5.0 V by an external voltage divider connected from OUT
ILOAD = 10mA
19 0 0- to ADJ. The ADP1711 is available with fixed output voltage
TIME (1ms/DIV)
31 06

options and features a bypass pin, which allows an external Figure 19. ADP1710 Adjustable Typical EN Pin Operation capacitor to be connected, which reduces internal reference noise. All devices are controlled by an enable pin (EN). Rev. 0 | Page 8 of 16 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADJUSTABLE OUTPUT VOLTAGE (ADP1710 ADJUSTABLE) BYPASS CAPACITOR (ADP1711) ENABLE FEATURE UNDERVOLTAGE LOCKOUT (UVLO) APPLICATION INFORMATION CAPACITOR SELECTION CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE