Preliminary Datasheet MB85RS4MTY (Fujitsu) - 10

MB85RS4MTY READ
The READ command reads FRAM memory cell array data. Arbitrary 24 bits address and op-code of READ are input to SI. The 5-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by con- tinuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK SI 0 0 0 0 0 0 1 1 X X X X X 18 17 16 5 4 3 2 1 0 Invalid MSB LSB MSB Data Out High-Z LSB SO 7 6 5 4 3 2 1 0 Invalid
WRITE
The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 24 bits of address and 8 bits of writing data are input to SI. The 5-bit upper address bit is invalid. When 8 bits of writing data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but if you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle can be continued infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data In SI 0 0 0 0 0 0 1 0 X X X X X 18 17 16 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB LSB MSB LSB High-Z SO
FSTRD
The FSTRD command reads FRAM memory cell array data. Arbitrary 24 bits address and op-code of FSTRD are input to SI followed by 8 bits dummy. The 5-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the FSTRD command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 29 30 31 32 33 38 39 40 41 42 43 44 45 46 47 SCK SI 0 0 0 0 1 0 1 1 X X X X X 18 17 16 2 1 0 X X X X Invalid MSB LSB MSB Data Out LSB High-Z SO 7 6 5 4 3 2 1 0 Invalid 10 DS501-00065-0v1-E Document Outline DESCRIPTION FEATURES PIN ASSIGNMENT PIN FUNCTIONAL DESCRIPTIONS BLOCK DIAGRAM SPI MODE SERIAL PERIPHERAL INTERFACE (SPI) STATUS REGISTER OP-CODE COMMAND BLOCK PROTECT WRITING PROTECT ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS 1. DC Characteristics 2. AC Characteristics 3. Pin Capacitance TIMING DIAGRAM POWER ON/OFF SEQUENCE FRAM CHARACTERISTICS NOTE ON USE ESD AND LATCH-UP REFLOW CONDITIONS AND FLOOR LIFE Current status on Contained Restricted Substances ORDERING INFORMATION PACKAGE DIMENSION MARKING (Example) PACKING INFORMATION 1. Tube 2. Emboss Tape