Datasheet AD9361 (Analog Devices) - 10

AD9361 Data Sheet CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) Table 5. 800 MHz, TDD Mode Parameter Min Typ Max Unit Test Conditions/Comments
1RX 5 MHz Bandwidth 180 mA Continuous RX 10 MHz Bandwidth 210 mA Continuous RX 20 MHz Bandwidth 260 mA Continuous RX 2RX 5 MHz Bandwidth 265 mA Continuous RX 10 MHz Bandwidth 315 mA Continuous RX 20 MHz Bandwidth 405 mA Continuous RX 1TX 5 MHz Bandwidth 7 dBm 340 mA Continuous TX −27 dBm 190 mA Continuous TX 10 MHz Bandwidth 7 dBm 360 mA Continuous TX −27 dBm 220 mA Continuous TX 20 MHz Bandwidth 7 dBm 400 mA Continuous TX −27 dBm 250 mA Continuous TX 2TX 5 MHz Bandwidth 7 dBm 550 mA Continuous TX −27 dBm 260 mA Continuous TX 10 MHz Bandwidth 7 dBm 600 mA Continuous TX −27 dBm 310 mA Continuous TX 20 MHz Bandwidth 7 dBm 660 mA Continuous TX −27 dBm 370 mA Continuous TX Rev. F | Page 10 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE