Datasheet AD9363 (Analog Devices) - 30

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AD9363 Data Sheet SPI INTERFACE AUXILIARY CONVERTERS
The AD9363 uses a serial peripheral interface (SPI) to communi-
AUXADC
cate with the BBP. The SPI can be configured as a 4-wire interface The AD9363 contains an auxiliary ADC that monitors system with dedicated receive and transmit ports, or it can be configured functions such as temperature or power output. The converter is as a 3-wire interface with a bidirectional data communication 12 bits wide and has an input range of 0.05 V to VDDA1P3_BB − port. This bus al ows the BBP to set al device control parameters 0.05 V. When enabled, the ADC is free running. SPI reads using a simple address data serial bus protocol. provide the last value latched at the ADC output. A multiplexer in Write commands fol ow a 24-bit format. The first six bits set the front of the ADC al ows the user to select between the AUXADC bus direction and number of bytes to transfer. The next 10 bits set input pin and a built-in temperature sensor. the address where data is to be written. The final eight bits are the
AUXDAC1 and AUXDAC2
data to be transferred to the specified register address (MSB to The AD9363 contains two identical auxiliary DACs that can LSB). The AD9363 also supports an LSB first format that al ows provide power amplifier (PA) bias or other system functionality. the commands to be written in LSB to MSB format. In this mode, The auxiliary DACs are 10 bits wide, have an output voltage range the register addresses are incremented for multibyte writes. of 0.5 V to VDD_GPO − 0.3 V and a current drive of 10 mA, and Read commands fol ow a similar format with the exception that can be directly control ed by the internal ENSM. the first 16 bits are transferred on the SPI_DI pin, and the final
POWERING THE AD9363
eight bits are read from the AD9363, either on the SPI_DO pin in 4-wire mode or on the SPI_DI pin in 3-wire mode. The AD9363 must be powered by the following three supplies:
CONTROL PINS
the analog supply (VDDx = 1.3 V), the interface supply (VDD_ INTERFACE = 1.8 V), and the GPO supply (VDD_GPO = 3.3 V).
Control Outputs (CTRL_OUT7 to CTRL_OUT0)
For applications requiring optimal noise performance, split and The AD9363 provides eight simultaneous real-time output source the 1.3 V analog supply from low noise, low dropout signals for use as interrupts to the BBP. These outputs can (LDO) regulators. Figure 42 shows the recommended method. be configured to output a number of internal settings and
3.3V
measurements that the BBP uses when monitoring trans-ceiver performance in different situations. The control output pointer
ADP2164 1.8V
register selects the information that is output to these pins, and the control output enable register determines which signals are
ADP1755 1.3V_A
activated for monitoring by the BBP. Signals used for manual 074
ADP1755
gain mode, calibration flags, state machine states, and the ADC
1.3V_B
10558- output are among the outputs that can be monitored on these Figure 42. Low Noise Power Solution for the AD9363 pins. For applications where board space is at a premium, and
Control Inputs (CTRL_IN3 to CTRL_IN0)
optimal noise performance is not an absolute requirement, The AD9363 provides four edge detected control input pins. In provide the 1.3 V analog rail directly from a switcher, and adopt manual gain mode, the BBP uses these pins to change the gain a more integrated power management unit (PMU) approach. table index in real time. Figure 43 shows this approach.
GPO PINS (GPO_3 TO GPO_0) ADP5040 ADP1755 1.3V VDDx LDO 1.2A
The AD9363 provides four 3.3 V capable general-purpose logic
BUCK AD9363
output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins
300mA 1.8V
control other peripheral devices such as regulators and switches
LDO VDD_INTERFACE
via the AD9363 SPI bus, or they function as slaves for the
300mA 3.3V VDD_GPO
internal AD9363 state machine.
LDO
075 10558- Figure 43. Space Optimized Power Solution for the AD9363 Rev. D | Page 30 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHZ FREQUENCY BAND 2.4 GHZ FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME and TX_FRAME Signals ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9363 APPLICATIONS INFORMATION PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE