Datasheet AD9364 (Analog Devices) - 6

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AD9364 Data Sheet Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 1.8 V DATA_CLK Clock Period tCP 16.276 ns 61.44 MHz DATA_CLK and FB_CLK Pulse tMP 45% of tCP 55% of tCP ns Width Tx Data TX_FRAME, P0_D, and P1_D Setup to FB_CLK tSTX 1 ns Hold to FB_CLK tHTX 0 ns DATA_CLK to Data Bus Output tDDRX 0 1.5 ns Delay DATA_CLK to RX_FRAME tDDDV 0 1.0 ns Delay Pulse Width ENABLE tENPW tCP ns TXNRX tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Bus Turnaround Time Before Rx tRPRE 2 × tCP ns TDD mode After Rx tRPST 2 × tCP ns TDD mode Capacitive Load 3 pF Capacitive Input 3 pF DIGITAL DATA TIMING (CMOS), VDD_INTERFACE = 2.5 V DATA_CLK Clock Period tCP 16.276 ns 61.44 MHz DATA_CLK and FB_CLK Pulse tMP 45% of tCP 55% of tCP ns Width Tx Data TX_FRAME, P0_D, and P1_D Setup to FB_CLK tSTX 1 ns Hold to FB_CLK tHTX 0 ns DATA_CLK to Data Bus Output tDDRX 0 1.2 ns Delay DATA_CLK to RX_FRAME tDDDV 0 1.0 ns Delay Pulse Width ENABLE tENPW tCP ns TXNRX tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Bus Turnaround Time Before Rx tRPRE 2 × tCP ns TDD mode After Rx tRPST 2 × tCP ns TDD mode Capacitive Load 3 pF Capacitive Input 3 pF DIGITAL DATA TIMING (LVDS) DATA_CLK Clock Period tCP 4.069 ns 245.76 MHz DATA_CLK and FB_CLK Pulse tMP 45% of tCP 55% of tCP ns Width Tx Data TX_FRAME and TX_D Setup to FB_CLK tSTX 1 ns Hold to FB_CLK tHTX 0 ns DATA_CLK to Data Bus Output tDDRX 0.25 1.25 ns Delay DATA_CLK to RX_FRAME tDDDV 0.25 1.25 ns Delay Pulse Width ENABLE tENPW tCP ns TXNRX tTXNRXPW tCP ns FDD independent ENSM mode TXNRX Setup to ENABLE tTXNRXSU 0 ns TDD ENSM mode Rev. C | Page 6 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide