Datasheet AD7293 (Analog Devices) - 23
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit Power Amplifier Current Controller with ADC, DACs, Temperature and Current Sensors |
| Seiten / Seite | 79 / 23 — Data Sheet. AD7293. ANALOG INPUTS. Pseudo Differential Mode. Single-Ended … |
| Revision | D |
| Dateiformat / Größe | PDF / 1.6 Mb |
| Dokumentensprache | Englisch |
Data Sheet. AD7293. ANALOG INPUTS. Pseudo Differential Mode. Single-Ended Mode. Differential Mode. ADC. REF p-p. IN+. AD72931. COMMON-MODE
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Data Sheet AD7293 ANALOG INPUTS Pseudo Differential Mode
The AD7293 has four analog inputs, VIN3 to VIN0. Depending The four uncommitted analog input channels can be configured on the configuration register setup, they can be configured as as two pseudo differential pairs. Two uncommitted inputs, VIN0 four single-ended inputs or two ful y differential channels. and VIN1, are a pseudo differential pair, as are VIN2 and VIN3. In
Single-Ended Mode
this mode, VIN+ is connected to the signal source, which can have a maximum amplitude of REFADC, 2 × REFADC, or 4 × REFADC, The AD7293 can have four single-ended analog input channels. depending on the range that is chosen, to make use of the full In applications where the signal source is high impedance, it is dynamic range of the device. A dc input is applied to VIN−. The recommended to buffer the analog input before applying it to the voltage applied to this input provides an offset from ground or a ADC. The analog input range is programmed to the fol owing pseudo ground for the VIN+ input. The ADC channel allocation modes: 0 V to REFADC, 0 V to 2 × REFADC, or 4 × REFADC mode. determines the channel specified as VIN+. The differential mode The voltage, with respect to AGND on the ADC analog input must be selected to operate in the pseudo differential mode. The pins, cannot exceed AVDD. resulting converted pseudo differential data is stored in twos
Differential Mode
complement format in the result register. The AD7293 can have two differential input pairs (VIN3 and VIN2, For VIN0, the governing equation for the pseudo differential VIN1 and VIN0). The amplitude of the differential signal is the mode is difference between the signals at VIN+ and VIN− (VIN0 and VIN1, VOUT = 2(VIN+ − VIN−) − REFADC or VIN3 and VIN2). Simultaneously drive VIN+ and VIN− by two signals, each of amplitude REF where: ADC, 2 × REFADC, or 4 × REFADC, depending on the range chosen, which are 180° out of phase. VIN+ is the single-ended signal. VIN− is a dc voltage. REFADC = 1.25 V.
ADC V REF p-p IN+ AD72931
The benefit of pseudo differential inputs is that they separate
COMMON-MODE VOLTAGE ADC V
the analog input signal ground from the ADC ground, allowing
REF p-p IN–
dc common-mode voltages to be cancelled. 039
1ADDITIONAL PINS OMITTED FOR CLARITY.
13016-
AD72931
Figure 37. Differential Input (VIN+/VIN− Refer to VIN0 to VIN3)
VREF p-p VIN+
Assuming that the 0 V to REFADC range is selected, the amplitude of the differential signal is, therefore, −REFADC to +REFADC peak to peak, regardless of the common-mode voltage (VCM).
VIN– DC INPUT
The common-mode voltage is the average of the two signals.
VOLTAGE
040 (V
1ADDITIONAL PINS OMITTED FOR CLARITY.
IN+ + VIN−)/2 13016- Figure 38. Pseudo Differential Input (V The common-mode voltage is the voltage on which the two IN+/VIN− Refer to VIN0 to VIN3) inputs are centered. The result is that the span of each input is
CURRENT SENSOR
VCM ± REFADC/2. This common-mode voltage must be set up Four bidirectional high-side current sense amplifiers are externally. provided that can accurately amplify differential current shunt When a conversion takes place, the common-mode voltage is voltages in the presence of high common-mode voltages from rejected, resulting in a virtually noise free signal of amplitude AVDD up to AVSS + 60 V. The current sensors can be read −REFADC to +REFADC, corresponding to the digital output codes directly, or optional y, they can be set to operate as part of the four of −2048 to +2047 in twos complement format. independent closed-loop, drain current controllers. See the When using the 2 × REF Closed-Loop Mode section for more information. ADC range, the input signal amplitude extends from −2 × REFADC (VIN+ = 0 V and VIN− = REFADC) to In open-loop operation, the current sense amplifiers measure +2 × REFADC (VIN− = 0 V and VIN+ = REFADC). the current through a shunt resistor. Each amplifier can accept Similarly, when using the 4 × REF differential inputs up to ±200 mV. A selectable gain amplifies ADC range, the input signal amplitude extends from −4 × REF the measured voltage drop across the current sensor. ADC (VIN+ = 0 V and VIN− = REFADC) to +4 × REFADC (VIN− = 0 V and VIN+ = REFADC). Rev. D | Page 23 of 79 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ADC DAC TEMPERATURE SENSOR CURRENT SENSOR CLOSED-LOOP SPECIFICATIONS GENERAL TIMING CHARACTERISTICS SPI Serial Interface Asynchronous Inputs Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTER (ADC) OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Pseudo Differential Mode CURRENT SENSOR Choosing the External Sense Resistor (RSENSE) TEMPERATURE SENSOR INTERNAL CHANNEL MONITORING DAC OPERATION Bipolar DACs Unipolar DACs DAC Enabling and Clamping Software Clamping: Internal ALERT0 Routing PMOS Drain Switch Control REFERENCE VDRIVE FEATURE OPEN-LOOP MODE CLOSED-LOOP MODE Adjustable Closed-Loop Setpoint Ramp Time Fast Ramp Feature Closed-Loop Sequencing Closed-Loop Integrator Programmable Voltage Limit Closed-Loop Range Upper Voltage Limit DIGITAL INPUT/OUTPUT REGISTERS LOAD DAC (LDAC PIN) Instantaneous DAC Updating (Asynchronous) Deferred DAC Updating (Synchronous) ALERTS AND LIMITS ALERTx Pins Software Alerts Page GPIO0 to GPIO3 Routing to ALERT1 AVDD AND AVSS ALARM MAXIMUM AND MINIMUM PAGES HYSTERESIS REGISTER SETTINGS REGISTERS COMMON TO ALL PAGES No Op Register (Register 0x00) Page Select Pointer Register (Register 0x01) Conversion Command (Register 0x02) Result Register (Register 0x03) DAC Enable Register (Register 0x04) GPIO Register (Register 0x05) Device ID Register (Register 0x0C) Software Reset Register (Register 0x0F) RESULT 0/DAC INPUT (PAGE 0x00) Voltage Input (VINx) Result Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEINT and TSENSEDx) Result Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Result Registers (Register 0x28 to Register 0x2B) DAC Input (UNI-VOUTx and BI-VOUTx) Registers (Register 0x30 to Register 0x37) RESULT 1 (PAGE 0x01) Voltage Supply Monitor Result Registers (Register 0x10 to Register 0x13) Bipolar DAC Internal Monitor Result (BI-VOUT0MON to BI-VOUT3MON) Registers (Register 0x14 to Register 0x17) RSx+MON Result Registers (Register 0x28 to Register 0x2B) CONFIGURATION (PAGE 0x02) Digital Output Enable Register (Register 0x11) Digital Input/Output Function Register (Register 0x12) Digital Functional Polarity Register (Register 0x13) General Register (Register 0x14) VINx Range x Registers (Register 0x15 and Register 0x16) VINx Differential/Single-Ended Enable Register (Register 0x17) VINx Filter Register (Register 0x18) VINx Background Enable Register (Register 0x19) Conversion Delay Register (Register 0x1A) Temperature Sensor (TSENSEx) Background Enable Register (Register 0x1B) Current Sensor (ISENSEx) Background Enable Register (Register 0x1C) Current Sensor (ISENSEx) Gain Register (Register 0x1D) DAC Snooze/SLEEP0 Pin Register (Register 0x1F) DAC Snooze/SLEEP1 Pin Register (Register 0x20) RSx+MON, Supply Monitor, BI-VOUTx Background Enable Register (Register 0x23) Integrator Limit and Closed-Loop Control Register (Register 0x28) PA_ON Control Register (Register 0x29) Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to Register 0x2D) Closed-Loop Fast Ramp and Integrator Time Constant Register (Register 0x2E) Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD Alarm Mask Register (Register 0x2F) SEQUENCE (PAGE 0x03) Voltage Input (VINx) Sequence Register (Register 0x10) Current Sensor (ISENSEx) and Temperature Sensor (TSENSEx) Sequence Register (Register 0x11) RSx+MON, Supply Monitor, and BI-VOUTx Monitor Sequence Register (Register 0x12) HIGH LIMIT 0 (PAGE 0x04) VINx High Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) High Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) High Limit Registers (Register 0x28 to Register 0x2B) HIGH LIMIT 1 (PAGE 0x05) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI) and AVSS High Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON High Limit Registers (Register 0x14 to Register 0x17) RSx+MON High Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 0 (PAGE 0x06) VINx Low Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Low Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Low Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 1 (PAGE 0x07) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Low Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Low Limit Registers (Register 0x14 to Register 0x17) RSx+MON Low Limit Registers (Register 0x28 to Register 0x2B) HYSTERESIS 0 (PAGE 0x08) VINx Hysteresis Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Hysteresis Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Hysteresis Registers (Register 0x28 to Register 0x2B) HYSTERESIS 1 (PAGE 0x09) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Hysteresis Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Hysteresis Registers (Register 0x14 to Register 0x17) RSx+MON Hysteresis Registers (Register 0x28 to Register 0x2B) MINIMUM 0 (PAGE 0x0A) VINx Minimum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Minimum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Minimum Registers (Register 0x28 to Register 0x2B) MINIMUM 1 (PAGE 0x0B) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Minimum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Minimum Registers (Register 0x14 to Register 0x17) RSx+MON Minimum Registers (Register 0x28 to Register 0x2B) MAXIMUM 0 (PAGE 0x0C) VINx Maximum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Maximum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Maximum Registers (Register 0x28 to Register 0x2B) MAXIMUM 1 (PAGE 0x0D) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Maximum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Maximum Registers (Register 0x14 to Register 0x17) RSx+MON Maximum Registers (Register 0x28 to Register 0x2B) OFFSET 0 (PAGE 0x0E) VINx Offset Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Offset Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Offset Registers (Register 0x28 to Register 0x2B) Unipolar DAC (UNI-VOUTx) Offset Registers (Register 0x30 to Register 0x33) Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to Register 0x37) OFFSET 1 (PAGE 0x0F) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Offset Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Offset Registers (Register 0x14 to Register 0x17) RSx+MON Offset Registers (Register 0x28 to Register 0x2B) ALERT (PAGE 0x10) Alert Summary (ALERTSUM) Register (Register 0x10) VINx Alert Register (Register 0x12) Temperature Sensor (TSENSEx) Alert Register (Register 0x14) Current Sensor (ISENSEx) Alert Register (Register 0x15) Supply and BI-VOUTxMON Alert Register (Register 0x18) RSx+MON Alert Register (Register 0x19) INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A) ALERT0 PIN ROUTING (PAGE 0x11) VINx ALERT0 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT0 Register (Register 0x14) Current Sensor (ISENSEx) ALERT0 Register (Register 0x15) Supply and BI-VOUTxMON ALERT0 Register (Register 0x18) RSx+MON ALERT0 Register (Register 0x19) INTLIMITx and AVss/AVDD ALERT0 Register (Register 0x1A) ALERT1 PIN ROUTING (PAGE 0x12) VINx ALERT1 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT1 Register (Register 0x14) Current Sensor (ISENSEx) ALERT1 Register (Register 0x15) Supply and BI-VOUTxMON ALERT1 Register (Register 0x18) RSx+MON ALERT1 Register (Register 0x19) INTLIMITx and AVSS/AVDD ALERT1 Register (Register 0x1A) SERIAL PORT INTERFACE INTERFACE PROTOCOL MODES OF OPERTION Background Mode (BG) Command Mode Current Sensor and Temperature Sensor Conversions Conversion Timing Current Sense and Temperature Sense Channel Integration Time Conversion and Integration Timing Example 1 Conversion and Integration Timing Example 2 Digital Filtering APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER CONTROL DEPLETION MODE AMPLIFIER BIASING AND PROTECTION LOOP COMPONENT SELECTION OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7293 ANALOG INPUTS Pseudo Differential Mode
The AD7293 has four analog inputs, VIN3 to VIN0. Depending The four uncommitted analog input channels can be configured on the configuration register setup, they can be configured as as two pseudo differential pairs. Two uncommitted inputs, VIN0 four single-ended inputs or two ful y differential channels. and VIN1, are a pseudo differential pair, as are VIN2 and VIN3. In
Single-Ended Mode
this mode, VIN+ is connected to the signal source, which can have a maximum amplitude of REFADC, 2 × REFADC, or 4 × REFADC, The AD7293 can have four single-ended analog input channels. depending on the range that is chosen, to make use of the full In applications where the signal source is high impedance, it is dynamic range of the device. A dc input is applied to VIN−. The recommended to buffer the analog input before applying it to the voltage applied to this input provides an offset from ground or a ADC. The analog input range is programmed to the fol owing pseudo ground for the VIN+ input. The ADC channel allocation modes: 0 V to REFADC, 0 V to 2 × REFADC, or 4 × REFADC mode. determines the channel specified as VIN+. The differential mode The voltage, with respect to AGND on the ADC analog input must be selected to operate in the pseudo differential mode. The pins, cannot exceed AVDD. resulting converted pseudo differential data is stored in twos
Differential Mode
complement format in the result register. The AD7293 can have two differential input pairs (VIN3 and VIN2, For VIN0, the governing equation for the pseudo differential VIN1 and VIN0). The amplitude of the differential signal is the mode is difference between the signals at VIN+ and VIN− (VIN0 and VIN1, VOUT = 2(VIN+ − VIN−) − REFADC or VIN3 and VIN2). Simultaneously drive VIN+ and VIN− by two signals, each of amplitude REF where: ADC, 2 × REFADC, or 4 × REFADC, depending on the range chosen, which are 180° out of phase. VIN+ is the single-ended signal. VIN− is a dc voltage. REFADC = 1.25 V.
ADC V REF p-p IN+ AD72931
The benefit of pseudo differential inputs is that they separate
COMMON-MODE VOLTAGE ADC V
the analog input signal ground from the ADC ground, allowing
REF p-p IN–
dc common-mode voltages to be cancelled. 039
1ADDITIONAL PINS OMITTED FOR CLARITY.
13016-
AD72931
Figure 37. Differential Input (VIN+/VIN− Refer to VIN0 to VIN3)
VREF p-p VIN+
Assuming that the 0 V to REFADC range is selected, the amplitude of the differential signal is, therefore, −REFADC to +REFADC peak to peak, regardless of the common-mode voltage (VCM).
VIN– DC INPUT
The common-mode voltage is the average of the two signals.
VOLTAGE
040 (V
1ADDITIONAL PINS OMITTED FOR CLARITY.
IN+ + VIN−)/2 13016- Figure 38. Pseudo Differential Input (V The common-mode voltage is the voltage on which the two IN+/VIN− Refer to VIN0 to VIN3) inputs are centered. The result is that the span of each input is
CURRENT SENSOR
VCM ± REFADC/2. This common-mode voltage must be set up Four bidirectional high-side current sense amplifiers are externally. provided that can accurately amplify differential current shunt When a conversion takes place, the common-mode voltage is voltages in the presence of high common-mode voltages from rejected, resulting in a virtually noise free signal of amplitude AVDD up to AVSS + 60 V. The current sensors can be read −REFADC to +REFADC, corresponding to the digital output codes directly, or optional y, they can be set to operate as part of the four of −2048 to +2047 in twos complement format. independent closed-loop, drain current controllers. See the When using the 2 × REF Closed-Loop Mode section for more information. ADC range, the input signal amplitude extends from −2 × REFADC (VIN+ = 0 V and VIN− = REFADC) to In open-loop operation, the current sense amplifiers measure +2 × REFADC (VIN− = 0 V and VIN+ = REFADC). the current through a shunt resistor. Each amplifier can accept Similarly, when using the 4 × REF differential inputs up to ±200 mV. A selectable gain amplifies ADC range, the input signal amplitude extends from −4 × REF the measured voltage drop across the current sensor. ADC (VIN+ = 0 V and VIN− = REFADC) to +4 × REFADC (VIN− = 0 V and VIN+ = REFADC). Rev. D | Page 23 of 79 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ADC DAC TEMPERATURE SENSOR CURRENT SENSOR CLOSED-LOOP SPECIFICATIONS GENERAL TIMING CHARACTERISTICS SPI Serial Interface Asynchronous Inputs Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTER (ADC) OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Pseudo Differential Mode CURRENT SENSOR Choosing the External Sense Resistor (RSENSE) TEMPERATURE SENSOR INTERNAL CHANNEL MONITORING DAC OPERATION Bipolar DACs Unipolar DACs DAC Enabling and Clamping Software Clamping: Internal ALERT0 Routing PMOS Drain Switch Control REFERENCE VDRIVE FEATURE OPEN-LOOP MODE CLOSED-LOOP MODE Adjustable Closed-Loop Setpoint Ramp Time Fast Ramp Feature Closed-Loop Sequencing Closed-Loop Integrator Programmable Voltage Limit Closed-Loop Range Upper Voltage Limit DIGITAL INPUT/OUTPUT REGISTERS LOAD DAC (LDAC PIN) Instantaneous DAC Updating (Asynchronous) Deferred DAC Updating (Synchronous) ALERTS AND LIMITS ALERTx Pins Software Alerts Page GPIO0 to GPIO3 Routing to ALERT1 AVDD AND AVSS ALARM MAXIMUM AND MINIMUM PAGES HYSTERESIS REGISTER SETTINGS REGISTERS COMMON TO ALL PAGES No Op Register (Register 0x00) Page Select Pointer Register (Register 0x01) Conversion Command (Register 0x02) Result Register (Register 0x03) DAC Enable Register (Register 0x04) GPIO Register (Register 0x05) Device ID Register (Register 0x0C) Software Reset Register (Register 0x0F) RESULT 0/DAC INPUT (PAGE 0x00) Voltage Input (VINx) Result Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEINT and TSENSEDx) Result Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Result Registers (Register 0x28 to Register 0x2B) DAC Input (UNI-VOUTx and BI-VOUTx) Registers (Register 0x30 to Register 0x37) RESULT 1 (PAGE 0x01) Voltage Supply Monitor Result Registers (Register 0x10 to Register 0x13) Bipolar DAC Internal Monitor Result (BI-VOUT0MON to BI-VOUT3MON) Registers (Register 0x14 to Register 0x17) RSx+MON Result Registers (Register 0x28 to Register 0x2B) CONFIGURATION (PAGE 0x02) Digital Output Enable Register (Register 0x11) Digital Input/Output Function Register (Register 0x12) Digital Functional Polarity Register (Register 0x13) General Register (Register 0x14) VINx Range x Registers (Register 0x15 and Register 0x16) VINx Differential/Single-Ended Enable Register (Register 0x17) VINx Filter Register (Register 0x18) VINx Background Enable Register (Register 0x19) Conversion Delay Register (Register 0x1A) Temperature Sensor (TSENSEx) Background Enable Register (Register 0x1B) Current Sensor (ISENSEx) Background Enable Register (Register 0x1C) Current Sensor (ISENSEx) Gain Register (Register 0x1D) DAC Snooze/SLEEP0 Pin Register (Register 0x1F) DAC Snooze/SLEEP1 Pin Register (Register 0x20) RSx+MON, Supply Monitor, BI-VOUTx Background Enable Register (Register 0x23) Integrator Limit and Closed-Loop Control Register (Register 0x28) PA_ON Control Register (Register 0x29) Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to Register 0x2D) Closed-Loop Fast Ramp and Integrator Time Constant Register (Register 0x2E) Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD Alarm Mask Register (Register 0x2F) SEQUENCE (PAGE 0x03) Voltage Input (VINx) Sequence Register (Register 0x10) Current Sensor (ISENSEx) and Temperature Sensor (TSENSEx) Sequence Register (Register 0x11) RSx+MON, Supply Monitor, and BI-VOUTx Monitor Sequence Register (Register 0x12) HIGH LIMIT 0 (PAGE 0x04) VINx High Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) High Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) High Limit Registers (Register 0x28 to Register 0x2B) HIGH LIMIT 1 (PAGE 0x05) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI) and AVSS High Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON High Limit Registers (Register 0x14 to Register 0x17) RSx+MON High Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 0 (PAGE 0x06) VINx Low Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Low Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Low Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 1 (PAGE 0x07) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Low Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Low Limit Registers (Register 0x14 to Register 0x17) RSx+MON Low Limit Registers (Register 0x28 to Register 0x2B) HYSTERESIS 0 (PAGE 0x08) VINx Hysteresis Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Hysteresis Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Hysteresis Registers (Register 0x28 to Register 0x2B) HYSTERESIS 1 (PAGE 0x09) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Hysteresis Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Hysteresis Registers (Register 0x14 to Register 0x17) RSx+MON Hysteresis Registers (Register 0x28 to Register 0x2B) MINIMUM 0 (PAGE 0x0A) VINx Minimum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Minimum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Minimum Registers (Register 0x28 to Register 0x2B) MINIMUM 1 (PAGE 0x0B) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Minimum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Minimum Registers (Register 0x14 to Register 0x17) RSx+MON Minimum Registers (Register 0x28 to Register 0x2B) MAXIMUM 0 (PAGE 0x0C) VINx Maximum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Maximum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Maximum Registers (Register 0x28 to Register 0x2B) MAXIMUM 1 (PAGE 0x0D) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Maximum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Maximum Registers (Register 0x14 to Register 0x17) RSx+MON Maximum Registers (Register 0x28 to Register 0x2B) OFFSET 0 (PAGE 0x0E) VINx Offset Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Offset Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Offset Registers (Register 0x28 to Register 0x2B) Unipolar DAC (UNI-VOUTx) Offset Registers (Register 0x30 to Register 0x33) Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to Register 0x37) OFFSET 1 (PAGE 0x0F) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Offset Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Offset Registers (Register 0x14 to Register 0x17) RSx+MON Offset Registers (Register 0x28 to Register 0x2B) ALERT (PAGE 0x10) Alert Summary (ALERTSUM) Register (Register 0x10) VINx Alert Register (Register 0x12) Temperature Sensor (TSENSEx) Alert Register (Register 0x14) Current Sensor (ISENSEx) Alert Register (Register 0x15) Supply and BI-VOUTxMON Alert Register (Register 0x18) RSx+MON Alert Register (Register 0x19) INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A) ALERT0 PIN ROUTING (PAGE 0x11) VINx ALERT0 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT0 Register (Register 0x14) Current Sensor (ISENSEx) ALERT0 Register (Register 0x15) Supply and BI-VOUTxMON ALERT0 Register (Register 0x18) RSx+MON ALERT0 Register (Register 0x19) INTLIMITx and AVss/AVDD ALERT0 Register (Register 0x1A) ALERT1 PIN ROUTING (PAGE 0x12) VINx ALERT1 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT1 Register (Register 0x14) Current Sensor (ISENSEx) ALERT1 Register (Register 0x15) Supply and BI-VOUTxMON ALERT1 Register (Register 0x18) RSx+MON ALERT1 Register (Register 0x19) INTLIMITx and AVSS/AVDD ALERT1 Register (Register 0x1A) SERIAL PORT INTERFACE INTERFACE PROTOCOL MODES OF OPERTION Background Mode (BG) Command Mode Current Sensor and Temperature Sensor Conversions Conversion Timing Current Sense and Temperature Sense Channel Integration Time Conversion and Integration Timing Example 1 Conversion and Integration Timing Example 2 Digital Filtering APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER CONTROL DEPLETION MODE AMPLIFIER BIASING AND PROTECTION LOOP COMPONENT SELECTION OUTLINE DIMENSIONS ORDERING GUIDE