Datasheet KSZ8895MQX, KSZ8895RQX KSZ8895FQX, KSZ8895MLX (Microchip) - 8

HerstellerMicrochip
BeschreibungIntegrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface
Seiten / Seite109 / 8 — KSZ8895MQX/RQX/FQX/MLX. TABLE 2-1:. SIGNALS - KSZ8895MQX/RQX/FQX/MLX …
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KSZ8895MQX/RQX/FQX/MLX. TABLE 2-1:. SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED). Type,. Pin. Note. Port. Pin Function, Note. 2-2. Number

KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Type, Pin Note Port Pin Function, Note 2-2 Number

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KSZ8895MQX/RQX/FQX/MLX TABLE 2-1: SIGNALS - KSZ8895MQX/RQX/FQX/MLX (CONTINUED) Type, Pin Pin Note Port Pin Function, Note 2-2 Number Name 2-1
3 VDDAR P — 1.2V analog VDD. 4 RXP1 I 1 Physical receive signal + (differential). 5 RXM1 I 1 Physical receive signal - (differential). 6 GNDA GND — Analog ground. 7 TXP1 O 1 Physical transmit signal + (differential). 8 TXM1 O 1 Physical transmit signal - (differential). 9 VDDAT P — 3.3V analog VDD. 10 RXP2 I 2 Physical receive signal + (differential). 11 RXM2 I 2 Physical receive signal - (differential). 12 GNDA GND — Analog ground. 13 TXP2 O 2 Physical transmit signal + (differential). 14 TXM2 O 2 Physical transmit signal - (differential). 15 VDDAR P — 1.2V analog VDD. 16 GNDA GND — Analog ground. Set physical transmit output current. Pull-down with a 17 ISET — — 12.4 kΩ 1% resistor. 18 VDDAT P — 3.3V analog VDD. 19 RXP3 I 3 Physical receive signal + (differential). 20 RXM3 I 3 Physical receive signal - (differential). 21 GNDA GND — Analog ground. 22 TXP3 O 3 Physical transmit signal + (differential). 23 TXM3 O 3 Physical transmit signal - (differential). 24 VDDAT P — 3.3V analog VDD. 25 RXP4 I 4 Physical receive signal + (differential). 26 RXM4 I 4 Physical receive signal - (differential). 27 GNDA GND — Analog ground. 28 TXP4 O 4 Physical transmit signal + (differential). 29 TXM4 O 4 Physical transmit signal - (differential). 30 GNDA GND — Analog ground. 31 VDDAR P — 1.2V analog VDD. 32 RXP5 I 5 Physical receive signal + (differential). DS00002246B-page 8

 2016 - 2019 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 RMII Timing 7.5 SPI Timing 7.6 Auto-Negotiation Timing 7.7 MDC/MDIO Timing 7.8 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service