Datasheet SZ8463ML, SZ8463RL, SZ8463FML, SZ8463FML (Microchip) - 9
| Hersteller | Microchip |
| Beschreibung | IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII |
| Seiten / Seite | 213 / 9 — KSZ8463ML/RL/FML/FRL. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE … |
| Dateiformat / Größe | PDF / 2.4 Mb |
| Dokumentensprache | Englisch |
KSZ8463ML/RL/FML/FRL. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 64-PIN LQFP ASSIGNMENT, (TOP VIEW). (TOP VIEW)
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KSZ8463ML/RL/FML/FRL 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 64-PIN LQFP ASSIGNMENT, (TOP VIEW)
FXSD1 RSTN P2LED0/GPIO10_MLI PSLED1/GPIO9_MLI P1LED0 P1LED1/GPIO7_MLI GPIO6 DGND VDD_IO GPIO5 GPIO4 GPIO3 GPIO2 VDD_L DGND GPIO1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RXM1 1 48 GPIO0 RXP1 2 47 GPIO11 AGND 3 46 GPIO8 TXM1 4 45 SPI_DI/MDIO TXP1 5 44 SPI_SCLK/MDC VDD_AL 6 43 INTRN
KSZ8463ML/RL/FML/FRL
ISET 7 42 SPI_CSN
(TOP VIEW)
AGND 8 41 SPI_DO VDD_A3.3 9 40 VDD_L RXM2 10 39 DGND RXP2 11 38 RX_CLK/GPIO7_RL1 AGND 12 37 COL/GPIO10_RL1 13 36 TXM2 CRS/GPIO9_RLI 14 35 TXP2 RXD0 34 FXSD2 15 RXD1 33 VDD_COL 16 RXD2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 X1 X2 DGNG TXEN TXD1 TXD0 DGND PWRDN VDD_IO VDD_IO RX_DV TXD2/NC TX_ER/MII_BP RXD3/REFCLK_O TX_CLK/REFCLK_I TXD3/EN_REFCLKO 2018 Microchip Technology Inc.
DS00002642A-page 9 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
FXSD1 RSTN P2LED0/GPIO10_MLI PSLED1/GPIO9_MLI P1LED0 P1LED1/GPIO7_MLI GPIO6 DGND VDD_IO GPIO5 GPIO4 GPIO3 GPIO2 VDD_L DGND GPIO1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RXM1 1 48 GPIO0 RXP1 2 47 GPIO11 AGND 3 46 GPIO8 TXM1 4 45 SPI_DI/MDIO TXP1 5 44 SPI_SCLK/MDC VDD_AL 6 43 INTRN
KSZ8463ML/RL/FML/FRL
ISET 7 42 SPI_CSN
(TOP VIEW)
AGND 8 41 SPI_DO VDD_A3.3 9 40 VDD_L RXM2 10 39 DGND RXP2 11 38 RX_CLK/GPIO7_RL1 AGND 12 37 COL/GPIO10_RL1 13 36 TXM2 CRS/GPIO9_RLI 14 35 TXP2 RXD0 34 FXSD2 15 RXD1 33 VDD_COL 16 RXD2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 X1 X2 DGNG TXEN TXD1 TXD0 DGND PWRDN VDD_IO VDD_IO RX_DV TXD2/NC TX_ER/MII_BP RXD3/REFCLK_O TX_CLK/REFCLK_I TXD3/EN_REFCLKO 2018 Microchip Technology Inc.
DS00002642A-page 9 Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service