Datasheet ADA4096-2, ADA4096-4 (Analog Devices) - 23

Data Sheet ADA4096-2/ADA4096-4 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.20 1.00 MAX 0.20 0.80 0.09 0.75 0.15 8° 0.60 SEATING 0.05 0° 0.30 0.45 PLANE COPLANARITY 0.19 0.10 A COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-
Figure 59. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
DETAIL A (JEDEC 95) 3.10 0.30 3.00 SQ 0.23 2.90 PIN 1 0.18 INDICATOR PIN 1 13 16 0.50 INDICATOR AREA OPTIONS (SEE DETAIL A) 12 1 BSC 1.75 EXPOSED 1.60 SQ PAD 1.45 9 4 8 5 0.50 0.20 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 0.80 FOR PROPER CONNECTION OF 0.75 TOP VIEW THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF E 2017- -005138 23- G K P COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 02-
Figure 60. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters Rev. G | Page 23 of 25 Document Outline Features Applications Pin Connection Diagrams General Description Revision History Specifications Electrical Specifications, VSY = ±1.5 V Electrical Specifications, VSY = ±5 V Electrical Specifications, VSY = ±15 V Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics ±1.5 V Characteristics ±5 V Characteristics ±15 V Characteristics Comparative Voltage and Variable Voltage Graphs Theory of Operation Input Stage Phase Inversion Input Overvoltage Protection Comparator Operation Outline Dimensions Ordering Guide Automotive Products