Preliminary Datasheet EPC2152 (Efficient Power Conversion) - 7
| Hersteller | Efficient Power Conversion |
| Beschreibung | 80 V, 12.5 A ePower Stage |
| Seiten / Seite | 15 / 7 — EPC2152 – 80 V, 12.5 A ePower™ Stage. PRELIMINARY. Truth Table. VDD. … |
| Dateiformat / Größe | PDF / 1.7 Mb |
| Dokumentensprache | Englisch |
EPC2152 – 80 V, 12.5 A ePower™ Stage. PRELIMINARY. Truth Table. VDD. VBOOT-VSW. HSin. LSin. HS FET. LS FET. Notes
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EPC2152 – 80 V, 12.5 A ePower™ Stage PRELIMINARY Truth Table VDD VBOOT-VSW HSin LSin HS FET LS FET
<UVLO - - - OFF OFF >UVLO <UVLO - 0 OFF OFF >UVLO <UVLO - 1 OFF ON (5) 0 0 OFF OFF 0 1 OFF ON >UVLO 1 0 ON OFF 1 1 BOTH ON (6)
Notes
Note 1: Output current rating is measured with Vin = 48 V, Vout = 12 V, PWM frequency = 1 MHz, PCB mounted using EPC90120 Eval Board, 800 LFM airflow, operating at ambient temperature of 25°C. Case temperature is measured on top of the die, with emissivity adjusted to 0.95, not to exceed 125°C at thermal equilibrium. Actual maximum output current depends on power dissipation, maximum allowed junction temperature, thermal management method and the operating environment. Note 2: Operating PWM switching frequency range is a function of power dissipation, maximum allowed junction temperature and minimum duty cycle. Running at higher PWM switching frequency lowers the maximum output current rating. Note 3: The output switching node (SW) is clamped by the LS FET negative source drain voltage in the 3rd quadrant with both HS and LS FETs in the off states during the deadtime period which is set by the application circuit with typical value of 10 ns. The time duration that the device can stay in the negative clamp voltage region is subjected to the amount of load current and maximum allowed junction temperature. Note 4: For logic input voltage above 5 V, a 5 kΩ resistor in series should be inserted to limit the input current into the logic input pins HSin and LSin. Note 5: LSin commands LS FET to turn-on to charge bootstrap supply through sync boot Note 6: Internal logic fol ows HSin, LSin respectively and does not lock-out when both HS and LS FETs are commanded to turn on together. Users need to implement shoot through prevention logic depending on application topology. Deadtime insertion circuit must not generate overlapping pulse widths shorter than minimum pulse width specifications, that might cause both HS and LS FETs to turn-on together.
Subject to Change without Notice www.epc-co.com COPYRIGHT 2020 Rev 1.1 Page 7
<UVLO - - - OFF OFF >UVLO <UVLO - 0 OFF OFF >UVLO <UVLO - 1 OFF ON (5) 0 0 OFF OFF 0 1 OFF ON >UVLO 1 0 ON OFF 1 1 BOTH ON (6)
Notes
Note 1: Output current rating is measured with Vin = 48 V, Vout = 12 V, PWM frequency = 1 MHz, PCB mounted using EPC90120 Eval Board, 800 LFM airflow, operating at ambient temperature of 25°C. Case temperature is measured on top of the die, with emissivity adjusted to 0.95, not to exceed 125°C at thermal equilibrium. Actual maximum output current depends on power dissipation, maximum allowed junction temperature, thermal management method and the operating environment. Note 2: Operating PWM switching frequency range is a function of power dissipation, maximum allowed junction temperature and minimum duty cycle. Running at higher PWM switching frequency lowers the maximum output current rating. Note 3: The output switching node (SW) is clamped by the LS FET negative source drain voltage in the 3rd quadrant with both HS and LS FETs in the off states during the deadtime period which is set by the application circuit with typical value of 10 ns. The time duration that the device can stay in the negative clamp voltage region is subjected to the amount of load current and maximum allowed junction temperature. Note 4: For logic input voltage above 5 V, a 5 kΩ resistor in series should be inserted to limit the input current into the logic input pins HSin and LSin. Note 5: LSin commands LS FET to turn-on to charge bootstrap supply through sync boot Note 6: Internal logic fol ows HSin, LSin respectively and does not lock-out when both HS and LS FETs are commanded to turn on together. Users need to implement shoot through prevention logic depending on application topology. Deadtime insertion circuit must not generate overlapping pulse widths shorter than minimum pulse width specifications, that might cause both HS and LS FETs to turn-on together.
Subject to Change without Notice www.epc-co.com COPYRIGHT 2020 Rev 1.1 Page 7