Datasheet SSD1306 (Solomon Systech) - 18

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Table 8-3 : Control pins of 8080 interface Function RD# WR# CS# D/C#
Write command H ↑ L L Read status ↑ H L L Write data H ↑ L H Read data ↑ H L H
Note
(1) ↑ stands for rising edge of signal (2) H stands for HIGH in signal (3) L stands for LOW in signal In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 8-4.
Figure 8-4 : Display data read back procedure - insertion of dummy read
WR# RD# Databus N n n+1 n+2 Write column Dummy read Read 1st data Read 2nd data Read 3rd data address
8.1.3 MCU Serial Interface (4-wire SPI)
The 4-wire serial interface consists of serial clock: SCLK, serial data: SDIN, D/C#, CS#. In 4-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to D7, E and R/W# (WR#)# can be connected to an external ground.
Table 8-4 : Control pins of 4-wire Serial interface Function E(RD#) R/W#(WR#) CS# D/C# D0
Write command Tie LOW Tie LOW L L ↑ Write data Tie LOW Tie LOW L H ↑
Note
(1) H stands for HIGH in signal (2) L stands for LOW in signal SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data RAM (GDDRAM) or command register in the same clock. Under serial mode, only write operations are allowed.
Solomon Systech
Aug 2010 P 18/64 Rev 1.5
SSD1306
Document Outline 1 GENERAL DESCRIPTION 2 FEATURES 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 DIE PAD FLOOR PLAN 6 PIN ARRANGEMENT 6.1 SSD1306TR1 pin assignment 7 PIN DESCRIPTION 8 FUNCTIONAL BLOCK DESCRIPTIONS 8.1 MCU Interface selection 8.1.1 MCU Parallel 6800-series Interface 8.1.2 MCU Parallel 8080-series Interface 8.1.3 MCU Serial Interface (4-wire SPI) 8.1.4 MCU Serial Interface (3-wire SPI) 8.1.5 MCU I2C Interface 8.1.5.1 I2C-bus Write data 8.1.5.2 Write mode for I2C 8.2 Command Decoder 8.3 Oscillator Circuit and Display Time Generator 8.4 FR synchronization 8.5 Reset Circuit 8.6 Segment Drivers / Common Drivers 8.7 Graphic Display Data RAM (GDDRAM) 8.8 SEG/COM Driving block 8.9 Power ON and OFF sequence 8.9.1 Power ON and OFF sequence with External VCC 8.9.2 Power ON and OFF sequence with Charge Pump Application 8.10 Charge Pump Regulator 9 COMMAND TABLE 9.1 Data Read / Write 10 COMMAND DESCRIPTIONS 10.1 Fundamental Command 10.1.1 Set Lower Column Start Address for Page Addressing Mode (00h~0Fh) 10.1.2 Set Higher Column Start Address for Page Addressing Mode (10h~1Fh) 10.1.3 Set Memory Addressing Mode (20h) 10.1.4 Set Column Address (21h) 10.1.5 Set Page Address (22h) 10.1.6 Set Display Start Line (40h~7Fh) 10.1.7 Set Contrast Control for BANK0 (81h) 10.1.8 Set Segment Re-map (A0h/A1h) 10.1.9 Entire Display ON (A4h/A5h) 10.1.10 Set Normal/Inverse Display (A6h/A7h) 10.1.11 Set Multiplex Ratio (A8h) 10.1.12 Set Display ON/OFF (AEh/AFh) 10.1.13 Set Page Start Address for Page Addressing Mode (B0h~B7h) 10.1.14 Set COM Output Scan Direction (C0h/C8h) 10.1.15 Set Display Offset (D3h) 10.1.16 Set Display Clock Divide Ratio/ Oscillator Frequency (D5h) 10.1.17 Set Pre-charge Period (D9h) 10.1.18 Set COM Pins Hardware Configuration (DAh) 10.1.19 Set VCOMH Deselect Level (DBh) 10.1.20 NOP (E3h) 10.1.21 Status register Read 10.1.22 Charge Pump Setting (8Dh) 10.2 Graphic Acceleration Command 10.2.1 Horizontal Scroll Setup (26h/27h) 10.2.2 Continuous Vertical and Horizontal Scroll Setup (29h/2Ah) 10.2.3 Deactivate Scroll (2Eh) 10.2.4 Activate Scroll (2Fh) 10.2.5 Set Vertical Scroll Area(A3h) 10.3 Advance Graphic Command 10.3.1 Set Fade Out and Blinking (23h) 10.3.2 Set Zoom In (D6h) 11 MAXIMUM RATINGS 12 DC CHARACTERISTICS 13 AC CHARACTERISTICS 14 Application Example 15 PACKAGE INFORMATION 15.1 SSD1306TR1 Detail Dimension 15.2 SSD1306Z2 Die Tray Information