Datasheet SSM2603 (Analog Devices) - 24

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SSM2603 Data Sheet AVDD HPVDD DCVDD DBVDD Mode PWROFF CLKOUT OSC OUT DAC ADC MIC LINEIN (3.3 V) (3.3 V) (3.3 V) (3.3 V) Unit
Sidetone 0 0 1 0 1 1 0 1 2.0 2.2 0.2 1.7 mA (Microphone-to- Line Output) Analog Bypass (Line 0 0 1 0 1 1 1 0 2.0 2.2 0.2 1.7 mA Input or Line Output) Power-Down 1 1 1 1 1 1 1 1 0.001 <0.001 0.03 0.03 mA
DIGITAL AUDIO I/F, ADDRESS 0x07 Table 26. Digital Audio I/F Register Bit Map D8 D7 D6 D5 D4 D3 D2 D1 D0
0 BCLKINV MS LRSWAP LRP WL[1:0] Format[1:0]
Table 27. Descriptions of Digital Audio I/F Register Bits Bit Name Description Settings
BCLKINV BCLK inversion control 0 = BCLK not inverted (default) 1 = BCLK inverted MS Master mode enable 0 = enable slave mode (default) 1 = enable master mode LRSWAP Swap DAC data control 0 = output left- and right-channel data as normal (default) 1 = swap left- and right-channel DAC data in audio interface LRP Polarity control for clocks in right-justified, 0 = normal PBLRC and RECLRC (default), or DSP Submode 1 left-justified, and I2S modes 1 = invert PBLRC and RECLRC polarity, or DSP Submode 2 WL[1:0] Data-word length control 00 = 16 bits 01 = 20 bits 10 = 24 bits (default) 11 = 32 bits Format[1:0] Digital audio input format control 00 = right justified 01 = left justified 10 = I2S mode (default) 11 = DSP mode
SAMPLING RATE, ADDRESS 0x08 Table 28. Sampling Rate Register Bit Map D8 D7 D6 D5 D4 D3 D2 D1 D0
0 CLKODIV2 CLKDIV2 SR[3:0] BOSR USB
Table 29. Descriptions of Sampling Rate Register Bits Bit Name Description Settings
CLKODIV2 CLKOUT divider select 0 = CLKOUT is core clock (default) 1 = CLKOUT is core clock divided by 2 CLKDIV2 Core clock divide select 0 = core clock is MCLK (default) 1 = core clock is MCLK divided by 2 SR[3:0] Clock setting condition See Table 30 and Table 31. BOSR Base oversampling rate USB mode: 0 = support for 250 fS based clock (default) 1 = support for 272 fS based clock Normal mode: 0 = support for 256 fS based clock (default) 1 = support for 384 fS based clock USB USB mode select 0 = normal mode enable (default) 1 = USB mode enable Rev. D | Page 24 of 31 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Digital Filter Characteristics Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Converter Filter Response Digital De-Emphasis Theory of Operation Digital Core Clock ADC and DAC ADC High-Pass and DAC De-Emphasis Filters Hardware Mute Pin Automatic Level Control (ALC) Decay (Gain Ramp-Up) Time Attack (Gain Ramp-Down) Time Noise Gate Analog Interface Signal Chain Stereo Line and Monaural Microphone Inputs Bypass and Sidetone Paths to Output Line and Headphone Outputs Digital Audio Interface Recording Mode Playback Mode Digital Audio Data Sampling Rate Software Control Interface Control Register Sequencing Typical Application Circuits Register Map Register Map Details Left-Channel ADC Input Volume, Address 0x00 Right-Channel ADC Input Volume, Address 0x01 Left-Channel DAC Volume, Address 0x02 Right-Channel DAC Volume, Address 0x03 Analog Audio Path, Address 0x04 Digital Audio Path, Address 0x05 Power Management, Address 0x06 Power Consumption Digital Audio I/F, Address 0x07 Sampling Rate, Address 0x08 Active, Address 0x09 Software Reset, Address 0x0F ALC Control 1, Address 0x10 ALC Control 2, Address 0x11 Noise Gate, Address 0x12 Outline Dimensions Ordering Guide