Datasheet MAX517, MAX518, MAX519 (Maxim) - 9

HerstellerMaxim
Beschreibung2-Wire, Serial, 8-Bit DACs with Rail-to-Rail Outputs
Seiten / Seite16 / 9 — 2-Wire Serial 8-Bit DACs with. Rail-to-Rail Outputs. …
Dateiformat / GrößePDF / 1.2 Mb
DokumentenspracheEnglisch

2-Wire Serial 8-Bit DACs with. Rail-to-Rail Outputs. MAX517/MAX518/MAX519. The Command Byte and Output Byte

2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX517/MAX518/MAX519 The Command Byte and Output Byte

Modelllinie für dieses Datenblatt

Textversion des Dokuments

2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs MAX517/MAX518/MAX519
SLAVE ADDRESS BYTE COMMAND BYTE OUTPUT BYTE SDA MSB LSB ACK MSB LSB ACK MSB LSB ACK SCL START CONDITION STOP CONDITION Figure 4. A Complete Serial Transmission R2 R1 R0 RST PD A0/0 ACK SDA X X SDA MSB LSB SCL SCL START CONDITION STOP CONDITION R2, R1, R0: RESERVED BITS. SET TO 0. RST: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS. Figure 5. All communications begin with a START condition and PD: POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4µA SHUTDOWN end with a STOP condition, both generated by a bus master. MODE. SET TO 0 TO RETURN TO THE NORMAL OPERATIONAL STATE. A0: ADDRESS BIT. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS SLAVE ADDRESS OF DATA IN THE NEXT BYTE. SET TO 0 FOR MAX517. ACK: ACKNOWLEDGE BIT. THE MAX517/MAX518/MAX519 PULLS SDA LOW DURING 0 1 0 1 or 1 or AD1 AD0 0 ACK THE 9TH CLOCK PULSE. AD3 AD2 SDA X: DON’T CARE. LSB Figure 7. Command Byte SCL SLAVE ADDRESS BITS AD0, AD1, AD2, AND AD3 CORRESPOND TO THE LOGIC STATE OF THE ADDRESS INPUT PINS. Figure 6. Address Byte these devices may share the bus. The MAX519 has 16 ignored. If an output byte follows the command byte, possible slave addresses. The eighth bit (LSB) in the A0 of the command byte indicates the digital address slave address byte should be low when writing to the of the DAC whose input data latch receives the digital MAX517/MAX518/MAX519. output data. Set this bit to 0 when writing to the The MAX517/MAX518/MAX519 monitor the bus continu- MAX517. The data is transferred to the DAC’s output ously, waiting for a START condition followed by their latch during the STOP condition following the transmis- slave address. When a device recognizes its slave sion. This allows both DACs of the MAX518/MAX519 to address, it is ready to accept data. be updated simultaneously (Figure 8). Setting the PD bit high powers down the MAX517/
The Command Byte and Output Byte
MAX518/MAX519 following a STOP condition (Figure A command byte follows the slave address. Figure 7 9a). If a command byte with PD set high is followed by shows the format for the command byte. A command an output byte, the addressed DAC’s input latch will be byte is usually followed by an output byte unless it is updated and the data will be transferred to the DAC’s the last byte in the transmission. If it is the last byte, all output latch following the STOP condition (Figure 9b). bits except PD (power-down) and RST (reset) are
_______________________________________________________________________________________ 9