Datasheet STTS22H (STMicroelectronics) - 10

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STTS22H I²C interface 5.2 I²C interface
Following the correct protocols the device will behave as an I²C slave. The registers embedded inside the ASIC device may be accessed through I²C serial interfaces. The transaction on the bus is started through a START signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH (referred to as an ST condition in the following paragraph). After this signal has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave (SAD subsequences). When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The address can be made up of a programmable part and a fixed part, thus allowing more than one device of the same type to be connected to the I²C bus (see Table 2. STTS22H address definition). Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse (SAK subsequence). A receiver which has been addressed is obliged to generate an acknowledge after each byte of data has been received. The I²C embedded inside the ASIC behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge has been returned (SAK), an 8-bit sub-address will be transmitted (SUB): the 7 LSB represent the actual register address while the MSB has no meaning. The IF_ADD_INC flag inside the CTRL register (11h) enables address auto increment, this flag is set by default to ‘1’, so the auto increment is active. If the IF_ADD_INC bit is ‘1’, the SUB (register address) will be automatically incremented to allow multiple data read/write at increasing addresses. Otherwise if the IF_ADD_INC bit is ‘0’, the SUB will remain unchanged and multiple read/write on the same address can be performed. If the LSB of the slave address was ‘1’ (read), a repeated START (SR) condition will have to be issued after the sub-address byte; if the LSB is ‘0’ (write) the Master will transmit to the slave with direction unchanged.
DS12606
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Rev 4 page 10/29
Document Outline 1 Overview 2 Pin description 3 Sensor parameters and electrical specifications 3.1 Sensor accuracy specifications 4 Absolute maximum ratings 5 Digital interfaces 5.1 SMBus interface 5.1.1 SMBus protocol 5.1.2 WRITE byte 5.1.3 READ byte 5.1.4 SEND byte 5.1.5 RECEIVE byte 5.1.6 SMBus timeout 5.1.7 Alert response address 5.2 I²C interface 5.2.1 I²C protocol 5.2.2 I²C read and write sequences 6 Register description 6.1 WHOAMI (01h) - RO 6.2 TEMP_H_LIMIT (02h) - RW 6.3 TEMP_L_LIMIT (03h) - RW 6.4 CTRL (04h) - RW 6.5 STATUS (05h) - RO 6.6 TEMP_L_OUT (06h) - RO 6.7 TEMP_H_OUT (07h) - RO 6.8 SOFTWARE_RESET (0Ch) - RW 7 Interrupt 8 ALERT / INT output 9 Operating modes 9.1 Enable sequence for one-shot mode 9.2 Enable sequence for freerun mode 9.3 Enable sequence for low-ODR mode 10 Package information 10.1 Soldering information 10.2 UDFN-6L package information 10.3 UDFN-6L packing information Revision history