Datasheet CMX7146 (CML Microcircuits) - 5

BPSK Wireless Data Modulator CMX7146
2 Signal List CMX7146 Signal 48-lead Type Description Q3 Name 1
MOSI OP SPI bus Master Output
2
EPSCLK BI SPI bus Serial Clock
3
MISO IP+PD SPI bus Master Input
4
EPCSN OP Flash/EEPROM Chip Select Used in conjunction with BOOTEN2 to determine the operation of
5
BOOTEN1 IP+PD the bootstrap program. Used in conjunction with BOOTEN1 to determine the operation of
6
BOOTEN2 IP+PD the bootstrap program.
7
DVss PWR Digital Ground C-BUS: A 'wire-ORable' output for connection to the Interrupt Request input of the host. Pulled down to VSS(D) when active and
8
IRQN OP is high impedance when inactive. An external pull-up resistor (R1) is required.

Internally generated 2.5V digital supply voltage. Must be decoupled to DVss by capacitors mounted close to the device
9
VDEC PWR pins. No other connections allowed, except for optional connection to RFVdd.
10
GPIO1 BI General Purpose I/O pin
11
GPIO3 BI General Purpose I/O pin
12
GPIO4 BI General Purpose I/O pin
13
SYSCLK1 OP Synthesized Digital System Clock Output 1
14
DVss PWR Digital Ground
15
GPIO2 BI General Purpose I/O pin
16
NC NC Do not connect
17
NC NC Do not connect
18
NC NC Do not connect
19
NC NC Do not connect
20
NC NC Do not connect
21
NC NC Do not connect
22
AVss PWR Analog Ground
23
MOD1 OP Modulator 1 output
24
MOD2 OP Modulator 2 output Internally generated bias voltage of about AVdd/2, except when the device is in ‘Powersave’ mode when VBIAS will discharge to
25
VBIAS OP AVss. Must be decoupled to AVss by a capacitor mounted close to the device pins. No other connections allowed.
26
AUDIO OUT OP Reserved for future use
27
AUXADC1 IP Auxiliary ADC input 1
28
AUXADC2 IP Auxiliary ADC input 2  2019 CML Microsystems Plc Page 5 D/7146/1 Document Outline Datasheet Front Page 1 Brief Description 1.1 History 2 Signal List 3 External Components 4 PCB Layout Guidelines and Power Supply Decoupling 5 General Description 5.1 CMX7146 Features 6 Detailed Descriptions 6.1 Xtal Frequency 6.2 Host Interface 6.2.1 C-BUS Operation 6.3 Function Image Loading 6.3.1 FI Loading from Host Controller 6.3.2 FI Loading from Flash/EEPROM 6.4 Device Control 6.4.1 Device Configuration (using the Programming Register) 6.4.2 Device Configuration (using dedicated registers) 6.4.3 Interrupt Operation 6.4.4 Signal Routing 6.4.5 Loading Transmit Data 6.4.6 The Transmit Sequence 6.4.7 Other Modem Modes 6.4.8 Data Transfer 6.4.9 Raw Data Transfer 6.4.10 Pre-loading transmit data 6.4.11 Auxiliary clock rates 6.4.12 Auxiliary data 6.4.13 GPIO Pin Operation 6.4.14 Auxiliary ADC Operation 6.4.15 Auxiliary DAC / RAMDAC Operation 6.5 Digital System Clock Generators 6.5.1 System Clock Operation 6.6 Signal Level Optimisation 6.7 C-BUS Register Summary 7 CMX7146 FI-1.x Features 7.1 Modulation 7.2 Radio Interface 7.3 Transmit Performance 8 Performance Specification 8.1 Electrical Performance 8.1.1 Absolute Maximum Ratings 8.1.2 Operating Limits 8.1.3 Operating Characteristics 8.1.4 Parametric Performance 8.2 C-BUS Timing 8.3 Packaging END OF DOCUMENT