Datasheet MAXM86161 (Maxim) - 29

MAXM86161 Single-Supply Integrated Optical Module for HR and SpO2 Measurement
Layout Guidelines
4) VREF and VLDO pins should be decoupled to the MAXM86161 is a high dynamic range analog front-end PCB GND plane with a 1.0μF ceramic capacitor. The (AFE) and its performance can be adversely impacted by voltage on the VREF pin is nominally 1.21V and that the physical printed circuit board (PCB) layout. See the for VLDO is nominally 1.8V, so a 6.3V rated ceramic below layout recommendations for detail. capacitor should be adequate for this purpose. 1) All bypass capacitors should be placed as close to 5) Shield the vias with board ground plane. the part as possible. 6) Use short and low resistance trace for VLED and all 2) All LEDx_DRV pins should be soldered down for GND. mechanical stability (the Maxim layout example has 7) All decoupling capacitors use individual vias to the three TPs for debug purposes only). PCB GND plane to avoid coupling between decou- 3) GND_ANA, GND_DIG, and PGND should be pled supplies when sharing vias. shorted to a single PCB GND plane. These three pins have been assigned along a single column so they can be easily shorted Figure 8. Layout Guideline www.maximintegrated.com Maxim Integrated │ 29 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information Electrical Characteristics Typical Operating Characteristics Pin Configuration Pin Description Detailed Description Optical Subsystem LED Driver FIFO Configuration LED Sequence Control (0x20 to 0x22) Pseudo-Code Example of Initialize the Optical AFE Pseudo-Code for Interrupt Handling with FIFO_A_FULL Pseudo-Code Example of Reading Data from FIFO Optical Timing One LED Pulsing with No Direct Ambient Sampling One LED Pulsing with Direct Ambient Sampling Two LEDs Pulsing Sequentially with Direct Ambient Sampling All LEDs Pulsing Sequentially with Direct Ambient Sampling ADC Architecture and Transfer Function Non-Linearity (XNL) Trim Proximity Mode Function Picket Fence Detect-and-Replace Function Layout Guidelines I2C/SMBus Compatible Serial Interface Detailed I2C Timing Diagram Bit Transfer START and STOP Conditions Early STOP Conditions Slave Address Acknowledge Bit I2C Write Data Format I2C Read Data Format Register Map Register Details INTERRUPT STATUS 1 (0x00) INTERRUPT STATUS 2 (0X01) INTERRUPT ENABLE 1 (0X02) INTERRUPT ENABLE 2 (0X03) FIFO WRITE POINTER (0X04) FIFO READ POINTER (0X05) OVER FLOW COUNTER (0X06) FIFO DATA COUNTER (0X07) FIFO DATA REGISTER (0X08) FIFO CONFIGURATION 1 (0X09) FIFO CONFIGURATION 2 (0X0A) SYSTEM CONTROL (0X0D) PPG SYNC CONTROL (0X10) PPG CONFIGURATION 1 (0X11) PPG CONFIGURATION 2 (0X12) PPG CONFIGURATION 3 (0X13) PROX INTERRUPT THRESHOLD (0X14) PHOTO DIODE BIAS (0X15) PICKET FENCE (0X16) LED SEQUENCE REGISTER 1 (0X20) LED SEQUENCE REGISTER 2 (0X21) LED SEQUENCE REGISTER 3 (0X22) LED1 PA (0x23) LED2 PA (0x24) LED3_PA (0x25) LED PILOT PA (0x29) LED RANGE 1 (0X2A) S1 HI RES DAC1 (0x2C) S2 HI RES DAC1 (0x2D) S3 HI RES DAC1 (0x2E) S4 HI RES DAC1 (0x2F) S5 HI RES DAC1 (0x30) S6 HI RES DAC1 (0x31) DIE TEMPERATURE CONFIGURATION (0X40) DIE TEMPERATURE INTEGER (0X41) DIE TEMPERATURE FRACTION (0X42) DAC CALIBRATION ENABLE (0X50) SHA COMMAND (0XF0) SHA CONFIGURATION (0XF1) MEMORY CONTROL (0XF2) MEMORY INDEX (0XF3) MEMORY DATA (0XF4) PART ID (0XFF) Ordering Information Revision History