Datasheet AD9272 (Analog Devices) - 5

link to page 7 link to page 7
AD9272 AD9272-40 AD9272-65 AD9272-80 Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Group Delay f = 1 MHz to ±2 ±2 ±2 ns Variation 18 MHz, GAIN+ = 0 V to 1.6 V Input-Referred LNA gain = 1.26/1.04/0.85 1.26/1.04/0.85 1.26/1.04/0.85 nV/√Hz Noise Voltage 15.6 dB/ 17.9 dB/ 21.3 dB, RFB = ∞ Noise Figure LNA gain = 15.6 dB/ 17.9 dB/ 21.3 dB Active Termina- RS = 50 Ω, 8.0/6.6/4.7 7.7/6.2/4.5 7.6/6.1/4.4 dB tion Matched RFB = 200 Ω/ 250 Ω/350 Ω Unterminated RFB = ∞ 4.7/3.7/2.8 4.6/3.6/2.8 4.5/3.6/2.7 dB Correlated Noise No signal, −30 −30 −30 dB Ratio correlated/ uncorrelated Output Offset −35 +35 −35 +35 −35 +35 LSB Signal-to-Noise fIN = 5 MHz at 65 64 63 dBFS Ratio (SNR) −10 dBFS, GAIN+ = 0 V fIN = 5 MHz at 57 56 54.5 dBFS −1 dBFS, GAIN+ = 1.6 V Harmonic Distortion Second fIN = 5 MHz at −62 −58 −55 dBc Harmonic −10 dBFS, GAIN+ = 0 V fIN = 5 MHz at −60 −61 −58 dBc −1 dBFS, GAIN+ = 1.6 V Third Harmonic fIN = 5 MHz at −71 −60 −60 dBc −10 dBFS, GAIN+ = 0 V fIN = 5 MHz at −57 −55 −56 dBc −1 dBFS, GAIN+ = 1.6 V Two-Tone IMD3 fIN1 = 5.0 MHz at −75 −75 −75 dBc (2 × F1 − F2) −1 dBFS, Distortion fIN2 = 5.01 MHz at −21 dBFS, GAIN+ = 1.6 V, LNA gain = 21.3 dB Channel-to-Channel fIN1 = 5.0 MHz at −1 −70 −70 −70 dB Crosstalk dBFS Overrange −65 −65 −65 dB condition4 Channel-to-Channel Full TGC path, 0.3 0.3 0.3 Degrees Delay Variation fIN = 5 MHz, GAIN+ = 0 V to 1.6 V PGA GAIN Differential input 21/24/27/30 21/24/27/30 21/24/27/30 dB to differential output Rev. C | Page 5 of 44 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE Caution RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE