Datasheet AD9277 (Analog Devices) - 4

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AD9277 SPECIFICATIONS AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 24 dB, GAIN− = 0.8 V, AAF LPF cutoff = fSAMPLE/4.5, HPF cutoff = LPF cutoff/20.7 (default), fSAMPLE = 50 MSPS (Register 0x02 = 0x01), full temperature, ANSI-644 LVDS mode, unless otherwise noted.
Table 1. Parameter1 Test Conditions/Comments Min Typ Max Unit
LNA CHARACTERISTICS Gain Single-ended input to differential output 15.6/17.9/21.3 dB Single-ended input to single-ended output 9.6/11.9/15.3 dB Input Voltage Range LNA output limited to 4.4 V p-p differential (Single-Ended) output LNA gain = 15.6 dB 733 mV p-p LNA gain = 17.9 dB 550 mV p-p LNA gain = 21.3 dB 367 mV p-p Input Common Mode (LI-x, LG-x) 1.0 V Output Common Mode (LO-x) 1.5 V Output Common Mode (LOSW-x) Switch off High-Z Ω Switch on 1.5 V Input Resistance (LI-x) RFB = 250 Ω 50 Ω RFB = 500 Ω 100 Ω RFB = ∞ 15 kΩ Input Capacitance (LI-x) 22 pF −3 dB Bandwidth 100 MHz Input Noise Voltage RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB 0.98 nV/√Hz LNA gain = 17.9 dB 0.86 nV/√Hz LNA gain = 21.3 dB 0.75 nV/√Hz Input Noise Current RFB = ∞ 1 pA/√Hz 1 dB Input Compression Point GAIN+ = 0 V LNA gain = 15.6 dB 1.0 V p-p LNA gain = 17.9 dB 0.8 V p-p LNA gain = 21.3 dB 0.5 V p-p Noise Figure RS = 50 Ω Active Termination Matched LNA gain = 15.6 dB, RFB = 200 Ω 4.8 dB LNA gain = 17.9 dB, RFB = 250 Ω 4.1 dB LNA gain = 21.3 dB, RFB = 350 Ω 3.2 dB Unterminated LNA gain = 15.6 dB, RFB = ∞ 3.4 dB LNA gain = 17.9 dB, RFB = ∞ 2.8 dB LNA gain = 21.3 dB, RFB = ∞ 2.3 dB FULL-CHANNEL (TGC) CHARACTERISTICS AAF Low-Pass Cutoff In Range −3 dB, programmable 8 18 MHz In Range AAF Bandwidth ±10 % Tolerance Group Delay Variation f = 1 MHz to 18 MHz, GAIN+ = 0 V to 1.6 V ±2 ns Input-Referred Noise Voltage GAIN+ = 1.6 V, RFB = ∞ LNA gain = 15.6 dB 1.26 nV/√Hz LNA gain = 17.9 dB 1.04 nV/√Hz LNA gain = 21.3 dB 0.85 nV/√Hz Rev. 0 | Page 4 of 48 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information TGC OPERATION Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode DIGITAL OUTPUTS AND TIMING SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE