Datasheet AD9648-EP (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter |
| Seiten / Seite | 17 / 10 — AD9648-EP. Enhanced Product. ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL … |
| Revision | B |
| Dateiformat / Größe | PDF / 309 Kb |
| Dokumentensprache | Englisch |
AD9648-EP. Enhanced Product. ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS. Parameter. Rating
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AD9648-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating
The exposed paddle must be soldered to the ground plane for Electrical the LFCSP package. Soldering the exposed paddle to the printed AVDD to AGND −0.3 V to +2.0 V circuit board (PCB) increases the reliability of the solder joints DRVDD to AGND −0.3 V to +2.0 V and maximizes the thermal capability of the package. VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V
Table 7. Thermal Resistance
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
Airflow
SYNC to DRVDD −0.3 V to AVDD + 0.2 V
Velocity 1, 2 1, 3 1, 4 1,2
VCM to AGND −0.3 V to AVDD + 0.2 V
Package Type (m/sec) θJA θJC θJB
Ψ
JT Unit
RBIAS to AGND −0.3 V to AVDD + 0.2 V 64-Lead LFCSP 0 22.3 1.4 11.8 0.1 °C/W 9 mm × 9 mm CSB to AGND −0.3 V to DRVDD + 0.2 V 1.0 19.5 N/A N/A 0.2 °C/W (CP-64-4) 2.5 17.5 N/A N/A 0.2 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. OEB −0.3 V to DRVDD + 0.2 V 2 Per JEDEC JESD51-2 (stil air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. PDWN −0.3 V to DRVDD + 0.2 V 4 Per JEDEC JESD51-8 (still air). D0A/D0B through D13A/D13B to −0.3 V to DRVDD + 0.2 V AGND Typical θJA is specified for a 4-layer PCB with a solid ground DCOA/DCOB to AGND −0.3 V to DRVDD + 0.2 V plane. As shown Table 7, airflow improves heat dissipation, Environmental which reduces θJA. In addition, metal in direct contact with the Operating Temperature Range −55°C to +125°C package leads from metal traces, through holes, ground, and (Ambient) power planes reduces θJA. Maximum Junction Temperature 150°C
ESD CAUTION
Under Bias Storage Temperature Range −65°C to +150°C (Ambient) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 10 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
AD9648-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating
The exposed paddle must be soldered to the ground plane for Electrical the LFCSP package. Soldering the exposed paddle to the printed AVDD to AGND −0.3 V to +2.0 V circuit board (PCB) increases the reliability of the solder joints DRVDD to AGND −0.3 V to +2.0 V and maximizes the thermal capability of the package. VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V
Table 7. Thermal Resistance
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
Airflow
SYNC to DRVDD −0.3 V to AVDD + 0.2 V
Velocity 1, 2 1, 3 1, 4 1,2
VCM to AGND −0.3 V to AVDD + 0.2 V
Package Type (m/sec) θJA θJC θJB
Ψ
JT Unit
RBIAS to AGND −0.3 V to AVDD + 0.2 V 64-Lead LFCSP 0 22.3 1.4 11.8 0.1 °C/W 9 mm × 9 mm CSB to AGND −0.3 V to DRVDD + 0.2 V 1.0 19.5 N/A N/A 0.2 °C/W (CP-64-4) 2.5 17.5 N/A N/A 0.2 °C/W SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V SDIO/DCS to AGND −0.3 V to DRVDD + 0.2 V 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. OEB −0.3 V to DRVDD + 0.2 V 2 Per JEDEC JESD51-2 (stil air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. PDWN −0.3 V to DRVDD + 0.2 V 4 Per JEDEC JESD51-8 (still air). D0A/D0B through D13A/D13B to −0.3 V to DRVDD + 0.2 V AGND Typical θJA is specified for a 4-layer PCB with a solid ground DCOA/DCOB to AGND −0.3 V to DRVDD + 0.2 V plane. As shown Table 7, airflow improves heat dissipation, Environmental which reduces θJA. In addition, metal in direct contact with the Operating Temperature Range −55°C to +125°C package leads from metal traces, through holes, ground, and (Ambient) power planes reduces θJA. Maximum Junction Temperature 150°C
ESD CAUTION
Under Bias Storage Temperature Range −65°C to +150°C (Ambient) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 10 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE