Datasheet AD4000, AD4004, AD4008 (Analog Devices)

HerstellerAnalog Devices
Beschreibung16-Bit, 500 kSPS, Precision, Pseudo Differential, SAR ADC
Seiten / Seite36 / 1 — 16-Bit, 2 MSPS/1 MSPS/500 kSPS,. Precision, Pseudo Differential, SAR …
RevisionC
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DokumentenspracheEnglisch

16-Bit, 2 MSPS/1 MSPS/500 kSPS,. Precision, Pseudo Differential, SAR ADCs. Data Sheet. AD4000/. AD4004/. AD4008. FEATURES

Datasheet AD4000, AD4004, AD4008 Analog Devices, Revision: C

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16-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Data Sheet AD4000/ AD4004/ AD4008 FEATURES
and AD4008 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs,
Throughput: 2 MSPS/1 MSPS/500 kSPS options
respectively. They incorporate ease of use features that reduce
INL: ±1.0 LSB maximum
signal chain power consumption, reduce signal chain complexity,
Guaranteed 16-bit, no missing codes
and enable higher channel density. The high-Z mode, coupled
Low power
with a long acquisition phase, eliminates the need for a dedicated
9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.5 mW at 500 kSPS
high power, high speed ADC driver, thus broadening the range
(VDD only)
of low power precision amplifiers that can drive these ADCs
70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
directly while still achieving optimum performance. The input
SNR: 93 dB typical at 1 kHz, VREF = 5 V; 90 dB typical at 100 kHz
span compression feature enables the ADC driver amplifier and
THD: −115 dB typical at 1 kHz, VREF = 5 V; −95 dB typical at 100 kHz
the ADC to operate off of common supply rails without the need
Ease of use features reduce system power and complexity
for a negative supply while preserving the full ADC code range.
Input overvoltage clamp circuit
The low serial peripheral interface (SPI) clock rate requirement
Reduced nonlinear input charge kickback
reduces the digital input/output power consumption, broadens
High-Z mode
processor options, and simplifies the task of sending data across
Long acquisition phase
digital isolation.
Input span compression
Operating from a 1.8 V supply, the AD4000/AD4004/AD4008
Fast conversion time allows low SPI clock rates
sample an analog input (IN+) from 0 V to VREF with respect to
SPI-programmable modes, read/write capability, status word
a ground sense (IN−) with VREF ranging from 2.4 V to 5.1 V.
Pseudo differential (single-ended) analog input range
The AD4000 consumes only 14 mW at 2 MSPS with a minimum
0 V to VREF with VREF from 2.4 V to 5.1 V
SCK rate of 70 MHz in turbo mode, the AD4004 consumes only
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
7 mW at 1 MSPS, and the AD4008 consumes only 3.5 mW at
SAR architecture: no latency/pipeline delay, valid first conversion
500 kSPS. The AD4000/AD4004/AD4008 all achieve ±1.0 LSB
First conversion accurate
integral nonlinearity error (INL) maximum, guaranteed no
Guaranteed operation: −40°C to +125°C
missing codes at 16 bits, and 93 dB signal-to-noise ratio (SNR)
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
for 1 kHz inputs. The reference voltage is applied externally and
Ability to daisy-chain multiple ADCs and busy indicator
can be set independently of the supply voltage.
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP APPLICATIONS
The SPI-compatible versatile serial interface features seven different modes including the ability, using the SDI input, to
Automatic test equipment
daisy-chain several ADCs on a single 3-wire bus, and provides
Machine automation Medical equipment
an optional busy indicator. The AD4000/AD4004/AD4008 are
Battery-powered equipment
compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the
Precision data acquisition systems
separate VIO supply.
GENERAL DESCRIPTION
The AD4000/AD4004 are available in a 10-lead MSOP and a 10-lead LFCSP, and the AD4008 is available in a 10-lead LFCSP, The AD4000/AD4004/AD4008 are low noise, low power, high with operation specified from −40°C to +125°C. The devices are speed, 16-bit, precision successive approximation register (SAR) pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8). analog-to-digital converters (ADCs). The AD4000, AD4004,
FUNCTIONAL BLOCK DIAGRAM 2.4V TO 5.1V 1.8V 10µF REF VDD AD4000/ VIO V 1.8V TO 5V REF HIGH-Z AD4004/ TURBO SDI VREF/2 MODE AD4008 MODE 0 IN+ SCK SERIAL 3-WIRE OR 4-WIRE 16-BIT INTERFACE SDO SPI INTERFACE SAR ADC (DAISY CHAIN, CS) IN– STATUS CNV CLAMP SPAN BITS COMPRESSION
001
GND
14956- Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS ANALOG INPUTS Input Overvoltage Clamp Circuit Switched Capacitor Input RC Filter Values DRIVER AMPLIFIER CHOICE High Frequency Input Signals Multiplexed Applications EASE OF DRIVE FEATURES Input Span Compression High-Z Mode Long Acquisition Phase VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE REGISTER READ/WRITE FUNCTIONALITY STATUS WORD CSB MODE, 3-WIRE TURBO MODE CSB MODE, 3-WIRE WITHOUT BUSY INDICATOR CSB MODE, 3-WIRE WITH BUSY INDICATOR CSB MODE, 4-WIRE TURBO MODE CSB MODE, 4-WIRE WITHOUT BUSY INDICATOR CSB MODE, 4-WIRE WITH BUSY INDICATOR DAISY-CHAIN MODE LAYOUT GUIDELINES EVALUATING THE AD4000/AD4004/AD4008 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE