Datasheet AD7768-1 (Analog Devices) - 77

Data Sheet AD7768-1 SPI INTERFACE DIAGNOSTIC CONTROL REGISTER Register: 0x28, Reset: 0x10, Name: SPI_DIAG_ENABLE Table 58. Bit Descriptions for SPI_DIAG_ENABLE Bit(s) Bit Name Description Reset Access
[7:5] Reserved Reserved 0x0 R 4 EN_ERR_SPI_IGNORE SPI ignore error enabled 0x1 R/W 3 EN_ERR_SPI_CLK_CNT SPI clock count error enabled. The SPI clock count error is only valid for SPI 0x0 R/W transactions that use CS. 2 EN_ERR_SPI_RD SPI read error enabled 0x0 R/W 1 EN_ERR_SPI_WR SPI write error enabled 0x0 R/W 0 Reserved Reserved 0x0 R
ADC DIAGNOSTIC FEATURE CONTROL REGISTER Register: 0x29, Reset: 0x07, Name: ADC_DIAG_ENABLE Table 59. Bit Descriptions for ADC_DIAG_ENABLE Bit(s) Bit Name Description Reset Access
[7:6] Reserved Reserved 0x0 R 5 EN_ERR_DLDO_PSM DLDO PSM error enabled 0x0 R/W 4 EN_ERR_ALDO_PSM ALDO PSM error enabled 0x0 R/W 3 EN_ERR_REF_DET Reference detect enable 0x0 R/W 2 EN_ERR_FILTER_SATURATED Filter saturated error enabled 0x1 R/W 1 EN_ERR_FILTER_NOT_SETTLED Filter not settled error enabled 0x1 R/W 0 EN_ERR_EXT_CLK_QUAL Enable qualification check on external clock 0x1 R/W
DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER Register: 0x2A, Reset: 0x0D, Name: DIG_DIAG_ENABLE Table 60. Bit Descriptions for DIG_DIAG_ENABLE Bit(s) Bit Name Description Reset Access
[7:5] Reserved Reserved 0x0 R 4 EN_ERR_MEMMAP_CRC Memory map CRC error enabled 0x0 R/W 3 EN_ERR_RAM_CRC RAM CRC error enabled 0x1 R/W 2 EN_ERR_FUSE_CRC Fuse CRC error enabled 0x1 R/W 1 Reserved Reserved 0x0 R/W 0 EN_FREQ_COUNT Enable MCLK counter 0x1 R/W
CONVERSION RESULT REGISTER Address: 0x2C, Reset: 0x000000, Name: ADC_DATA Table 61. Bit Descriptions for ADC_DATA Bit(s) Bit Name Description Reset Access
[23:16] ADC_READ_DATA[23:16] ADC read data 0x0 R [15:8] ADC_READ_DATA[15:8] ADC read data 0x0 R [7:0] ADC_READ_DATA[7:0] ADC read data 0x0 R Rev. A | Page 77 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE