Datasheet GS66508T (GaN Systems) - 13

GS66508T Top-side cooled 650 V E-mode GaN transistor Preliminary Datasheet
Routing Guidelines
The following layout recommendations are highlighted. Additional detail is provided in Application Note GN001 at www.gansystems.com. Keep out area: Avoid placing traces or vias on the top layer of the PCB, directly underneath the GS66508T package. This is to prevent potential electro-migration and solder mask isolation issues during high temperature or/and voltage operation. Symmetrical dual gates are provided for flexible layout and easy paralleling. Either gate drive can be used. If the second gate is note used, it should be left floating. A separate Source Sense pin is not provided on our top-side products because of the ultra-low inductance of our GaNPX® packaging. The Source Sense pin functionality can be implemented simply by routing a Kelvin connection at the side of the Source pad. This can be done at either side of the source pad for layout optimization. Rev 180424 © 2009-2018 GaN Systems Inc. 13 This information pertains to a product under development. Its characteristics and specifications are subject to change without notice. Submit datasheet feedback