X9418 Datasheet (Renesas) - 8

HerstellerRenesas
BeschreibungLow Noise/Low Power/2-Wire Bus
Seiten / Seite20 / 8 — Figure 8. Detailed Potentiometer Block Diagram. DETAILED OPERATION. Data …
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Figure 8. Detailed Potentiometer Block Diagram. DETAILED OPERATION. Data Registers. Wiper Counter Register

Figure 8 Detailed Potentiometer Block Diagram DETAILED OPERATION Data Registers Wiper Counter Register

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X9418
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path Serial VH/RH Bus From Interface Circuitry Input C Register 0 Register 1 o u n 8 6 Parallel t Bus e Input r Wiper Register 2 Register 3 Counter D Register e c (WCR) o d e INC/DEC Logic If WCR = 00[H] then VW/RW = VL/RL UP/DN UP/DN If WCR = 3F[H] then VW/RW = VH/RH Modified SCL V CLK L/RL VW/RW
DETAILED OPERATION Data Registers
Both XDCP potentiometers share the serial interface Each potentiometer has four nonvolatile Data Registers. and share a common architecture. Each potentiometer These can be read or written directly by the host and has a Wiper Counter Register and four Data Registers. data can be transferred between any of the four Data A detailed discussion of the register organization and Registers and the Wiper Counter Register. It should be array operation follows. noted all operations changing data in one of these registers is a nonvolatile operation and will take a
Wiper Counter Register
maximum of 10ms. The X9418 contains two wiper counter registers, one for If the application does not require storage of multiple each XDCP potentiometer. The Wiper Counter Register settings for the potentiometer, these registers can be can be envisioned as a 6-bit parallel and serial load used as regular memory locations that could possibly counter with its outputs decoded to select one of sixty- store system parameters or user preference data. four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written
Register Descriptions
directly by the host via the write Wiper Counter Register
Data Registers, (6-Bit), Nonvolatile
instruction (serial load); it may be written indirectly by D5 D4 D3 D2 D1 D0 transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel NV NV NV NV NV NV load); it can be modified one step at a time by the (MSB) (LSB) Increment/Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon Four 6-bit Data Registers for each XDCP. (eight 6-bit power-up. registers in total). The WCR is a volatile register; that is, its contents are – {D5~D0}: These bits are for general purpose not lost when the X9418 is powered-down. Although the volatile data storage or for storage of up to four register is automatically loaded with the value in DR0 different wiper values. The contents of Data Register 0 upon power-up, it should be noted this may be different are automatically moved to the Wiper Counter from the value present at power-down. Register on power-up. FN8194 Rev 2.00 Page 8 of 20 October 12, 2006