Datasheet LT1351 (Analog Devices) - 10

LT1351
U U W U APPLICATIONS INFORMATION
noise gain is one and a large feedback resistor is used, C
Shutdown
F should be greater than or equal to CIN. An example would The LT1351 has a Shutdown pin for conserving power. be an I-to-V converter as shown in the Typical Applications When this pin is open or 2V above the negative supply the section. part operates normally. When pulled down to V – the supply current will drop to about 10µA. The current out of
Capacitive Loading
the Shutdown pin is also typically 10µA. In shutdown the The LT1351 is stable with any capacitive load. As the amplifier output is not isolated from the inputs so the capacitive load increases, both the bandwidth and phase LT1351 cannot be used in multiplexing applications using margin decrease so there will be peaking in the frequency the shutdown feature. domain and in the transient response. Graphs of Fre- A level shift application is shown in the Typical Applica- quency Response vs Capacitive Load, Capacitive Load tions section so that a ground-referenced logic signal can Handling and the transient response photos clearly show control the Shutdown pin. these effects.
Circuit Operation Input Considerations
The LT1351 circuit topology is a true voltage feedback Each of the LT1351 inputs is the base of an NPN and amplifier that has the slewing behavior of a current a PNP transistor whose base currents are of opposite feedback amplifier. The operation of the circuit can be polarity and provide first-order bias current cancellation. understood by referring to the simplified schematic. Because of variation in the matching of NPN and PNP beta, the polarity of the input bias current can be positive The inputs are buffered by complementary NPN and PNP or negative. The offset current does not depend on emitter followers which drive R1, a 1k resistor. The input NPN/PNP beta matching and is well controlled. The use of voltage appears across the resistor generating currents balanced source resistance at each input is recommended which are mirrored into the high impedance node and for applications where DC accuracy must be maximized. compensation capacitor CT. Complementary followers form an output stage which buffers the gain node from The inputs can withstand transient differential input volt- the load. The output devices Q19 and Q22 are connected ages up to 10V without damage and need no clamping or to form a composite PNP and composite NPN. source resistance for protection. Differential inputs, how- ever, generate large supply currents (tens of mA) as The bandwidth is set by the input resistor and the required for high slew rates. If the device is used with capacitance on the high impedance node. The slew rate sustained differential inputs, the average supply current is determined by the current available to charge the will increase, excessive power dissipation will result and capacitance. This current is the differential input voltage the part may be damaged. The part should not be used as divided by R1, so the slew rate is proportional to the a comparator, peak detector or other open-loop applica- input. Highest slew rates are therefore seen in the lowest tion with large, sustained differential inputs. Under gain configurations. For example, a 10V output step in a normal, closed-loop operation, an increase of power gain of 10 has only a 1V input step whereas the same dissipation is only noticeable in applications with large output step in unity gain has a 10 times greater input step. slewing outputs and is proportional to the magnitude of The curve of Slew Rate vs Input Level illustrates this the differential input voltage and the percent of the time relationship. that the inputs are apart. Measure the average supply Capacitive load compensation is provided by the RC, CC current for the application in order to calculate the power network which is bootstrapped across the output stage. dissipation. When the amplifier is driving a light load the network has no effect. When driving a capacitive load (or a low value 10