Datasheet LT1192 (Analog Devices) - 4
| Hersteller | Analog Devices |
| Beschreibung | Ultrahigh Speed Operational Amplifier |
| Seiten / Seite | 12 / 4 — ELECTRICAL CHARACTERISTICS The. denotes the specifications which apply … |
| Dateiformat / Größe | PDF / 259 Kb |
| Dokumentensprache | Englisch |
ELECTRICAL CHARACTERISTICS The. denotes the specifications which apply over the full operating. temperature range of 0
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LT1192
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range of 0
°
C
≤
TA
≤
70
°
C. VS =
±
5V, Pin 5 open circuit unless otherwise noted. LT1191C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage N8 Package ● 0.4 3 mV SO-8 Package 4 mV ∆VOS/∆T Input VOS Drift ● 2 µV/°C IOS Input Offset Current ● 0.2 1.7 µA IB Input Bias Current ● ±0.5 ±2.5 µA CMRR Common Mode Rejection Ratio VCM = – 2.5V to 3.5V ● 68 85 dB PSRR Power Supply Rejection Ratio VS = ±2.375V to ±5V ● 70 90 dB AVOL Large-Signal Voltage Gain RL = 1k, VO = ±3V ● 90 140 V/mV RL = 100Ω, VO = ±3V ● 10 30 V/mV VOUT Output Voltage Swing RL = 1k ● ±3.7 ±3.9 V IS Supply Current ● 32 38 mA Shutdown Supply Current Pin 5 at V – (Note 8) ● 1.4 2.1 mA ISHDN Shutdown Pin Current Pin 5 at V – ● 20 µA
Note 1:
Absolute Maximum Ratings are those values beyond which the
Note 6:
Settling time measurement techniques are shown in “Take the life of the device may be impaired. Guesswork Out of Settling Time Measurements,” EDN, September 19,
Note 2:
A heat sink is required to keep the junction temperature below 1985. AV = –5, RL = 1k. absolute maximum when the output is shorted.
Note 7:
NTSC (3.58MHz). For RL = 1k, Diff AV = 0.1%, Diff Ph = 0.01°.
Note 3:
Exceeding the input common mode range may cause the output Diff AV and Diff Ph can be reduced for AV < 10. to invert.
Note 8:
See Applications section for shutdown at elevated temperatures.
Note 4:
Slew rate is measured between ±1V on the output, with a ±0.3V Do not operate the shutdown above TJ > 125°C. input step.
Note 9
: AC parameters are 100% tested on the ceramic and plastic DIP
Note 5:
Full-power bandwidth is calculated from the slew rate packaged parts (J and N suffix) and are sample tested on every lot of the measurement: SO packaged parts (S suffix). FPBW = SR/2πVP.
Optional Offset Nulling Circuit
5V 3 + 7 6 LT1192 2 – 4 8 –5V 1 INPUT OFFSET VOLTAGE CAN BE ADJUSTED OVER A ±20mV RANGE WITH A 1k TO 10k POTENTIOMETER Ω Ω LT1192 • TA03 4
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range of 0
°
C
≤
TA
≤
70
°
C. VS =
±
5V, Pin 5 open circuit unless otherwise noted. LT1191C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage N8 Package ● 0.4 3 mV SO-8 Package 4 mV ∆VOS/∆T Input VOS Drift ● 2 µV/°C IOS Input Offset Current ● 0.2 1.7 µA IB Input Bias Current ● ±0.5 ±2.5 µA CMRR Common Mode Rejection Ratio VCM = – 2.5V to 3.5V ● 68 85 dB PSRR Power Supply Rejection Ratio VS = ±2.375V to ±5V ● 70 90 dB AVOL Large-Signal Voltage Gain RL = 1k, VO = ±3V ● 90 140 V/mV RL = 100Ω, VO = ±3V ● 10 30 V/mV VOUT Output Voltage Swing RL = 1k ● ±3.7 ±3.9 V IS Supply Current ● 32 38 mA Shutdown Supply Current Pin 5 at V – (Note 8) ● 1.4 2.1 mA ISHDN Shutdown Pin Current Pin 5 at V – ● 20 µA
Note 1:
Absolute Maximum Ratings are those values beyond which the
Note 6:
Settling time measurement techniques are shown in “Take the life of the device may be impaired. Guesswork Out of Settling Time Measurements,” EDN, September 19,
Note 2:
A heat sink is required to keep the junction temperature below 1985. AV = –5, RL = 1k. absolute maximum when the output is shorted.
Note 7:
NTSC (3.58MHz). For RL = 1k, Diff AV = 0.1%, Diff Ph = 0.01°.
Note 3:
Exceeding the input common mode range may cause the output Diff AV and Diff Ph can be reduced for AV < 10. to invert.
Note 8:
See Applications section for shutdown at elevated temperatures.
Note 4:
Slew rate is measured between ±1V on the output, with a ±0.3V Do not operate the shutdown above TJ > 125°C. input step.
Note 9
: AC parameters are 100% tested on the ceramic and plastic DIP
Note 5:
Full-power bandwidth is calculated from the slew rate packaged parts (J and N suffix) and are sample tested on every lot of the measurement: SO packaged parts (S suffix). FPBW = SR/2πVP.
Optional Offset Nulling Circuit
5V 3 + 7 6 LT1192 2 – 4 8 –5V 1 INPUT OFFSET VOLTAGE CAN BE ADJUSTED OVER A ±20mV RANGE WITH A 1k TO 10k POTENTIOMETER Ω Ω LT1192 • TA03 4