Datasheet LT1468 (Analog Devices) - 11

LT1468
APPLICATIONS INFORMATION Input Considerations Total Input Noise
Each input of the LT1468 is protected with a 100Ω series The curve of Total Noise vs Unmatched Source Resistance resistor and back-to-back diodes across the bases of the in the Typical Performance Characteristics shows that input devices. If the inputs can be pulled apart, the input with source resistance below 1k, the voltage noise of the current should be limited to less than 10mA with an ex- amplifi er dominates. In the 1k to 20k region the increase ternal series resistor. Each input also has two ESD clamp in noise is due to the source resistance. Above 20k the diodes—one to each supply. If an input is driven above input current noise component is larger than the resistor the supply, limit the current with an external resistor to noise. less than 10mA.
Capacitive Loading
The LT1468 employs bias current cancellation at the inputs. The inverting input current is trimmed at zero common The LT1468 drives capacitive loads of up to 100pF in unity mode voltage to minimize errors in inverting applications gain and 300pF in a gain of –1. When there is a need to such as I-to-V converters. The noninverting input current drive a larger capacitive load, a small series resistor should is not trimmed and has a wider variation and therefore a be inserted between the output and the load. In addition, larger maximum value. As the input offset current can be a capacitor should be added between the output and the greater than either input current, the use of balanced source inverting input as shown in Driving Capacitive Loads. resistance is NOT recommended as it actually degrades DC accuracy and also increases noise.
Settling Time
The input bias currents vary with common mode voltage The LT1468 is a single stage amplifi er with an optimal as shown in the Typical Performance Characteristics. thermal layout that leads to outstanding settling The cancellation circuitry was not designed to track this performance. Measuring settling, even at the 12-bit level common mode voltage because the settling time would is very challenging, and at the 16-bit level requires a great have been adversely affected. deal of subtlety and expertise. Fortunately, there are two excellent Linear Technology reference sources for settling The LT1468 inputs can be driven to the negative supply measurements, Application Notes 47 and 74. Appendix B and to within 0.5V of the positive supply without phase of AN47 is a vital primer on 12-bit settling measurements, reversal. As the input moves closer than 0.5V to the posi- and AN74 extends the state of the art while concentrating tive supply, the output reverses phase. on settling time with a 16-bit current output DAC input.
Input Stage Protection Driving Capacitive Loads
RF CF RO ≥ (1 + RF/RG)/(2πCL5MHz) R R1 R2 F ≥ 10RO RG C 100Ω 100Ω F = (2RO/RF)CL Q1 Q2 – +IN –IN RO LT1468 VOUT 1468 AI03 VIN + CL 1468 AI04 1468fb 11