Datasheet LT1800 (Analog Devices) - 12
| Hersteller | Analog Devices |
| Beschreibung | 80MHz, 25V/µs Low Power Rail-to-Rail Input and Output Precision Op Amp |
| Seiten / Seite | 18 / 12 — APPLICATIONS INFORMATION. Circuit Description. Power Dissipation. Figure … |
| Dateiformat / Größe | PDF / 285 Kb |
| Dokumentensprache | Englisch |
APPLICATIONS INFORMATION. Circuit Description. Power Dissipation. Figure 1. LT1800 Simplifi ed Schematic Diagram
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LT1800
APPLICATIONS INFORMATION Circuit Description
A pair of complementary common emitter stages Q14/Q15 that enable the output to swing from rail to rail constructs The LT1800 has an input and output signal range that cov- the output stage. The capacitors C2 and C3 form the lo- ers from the negative power supply to the positive power cal feedback loops that lower the output impedance at supply. Figure 1 depicts a simplifi ed schematic of the high frequency. These devices are fabricated on Linear amplifi er. The input stage is comprised of two differential Technology’s proprietary high speed complementary amplifi ers, a PNP stage Q1/Q2 and an NPN stage Q3/Q4 bipolar process. that are active over the different ranges of common mode input voltage. The PNP differential pair is active between the
Power Dissipation
negative supply to approximately 1.2V below the positive supply. As the input voltage moves closer toward the posi- The LT1800 amplifi er is offered in a small package, SOT-23, tive supply, the transistor Q5 will steer the tail current I which has a thermal resistance of 250°C/W, θ 1 to JA. So there is the current mirror Q6/Q7, activating the NPN differential a need to ensure that the die’s junction temperature should pair and the PNP pair becomes inactive for the rest of the not exceed 150°C. Junction temperature TJ is calculated input common mode range up to the positive supply. Also from the ambient temperature TA, power dissipation PD at the input stage, devices Q17 to Q19 act to cancel the bias and thermal resistance θJA: current of the PNP input pair. When Q1-Q2 are active, the TJ = TA + (PD • θJA) current in Q16 is controlled to be the same as the current in Q1-Q2, thus the base current of Q16 is nominally equal The power dissipation in the IC is the function of the sup- to the base current of the input devices. The base current ply voltage, output voltage and the load resistance. For of Q16 is then mirrored by devices Q17-Q19 to cancel the a given supply voltage, the worst-case power dissipation base current of the input devices Q1-Q2. PDMAX occurs at the maximum supply current and the V+ R3 R4 R5 V+ V– + + Q12 D1 ESDD1 ESDD2 Q11 Q13 Q15 I I 2 1 C2 +IN + D6 D8 Q5 VBIAS D2 I3 OUT D5 D7 CC V– –IN Q4 Q3 Q1 Q2 D3 ESDD4 ESDD3 BUFFER AND Q10 OUTPUT BIAS V+ V– D4 Q9 Q8 Q16 C1 Q17 Q18 Q19 Q7 Q6 Q14 R1 R2 V– 1800 F01
Figure 1. LT1800 Simplifi ed Schematic Diagram
1800fa 12
APPLICATIONS INFORMATION Circuit Description
A pair of complementary common emitter stages Q14/Q15 that enable the output to swing from rail to rail constructs The LT1800 has an input and output signal range that cov- the output stage. The capacitors C2 and C3 form the lo- ers from the negative power supply to the positive power cal feedback loops that lower the output impedance at supply. Figure 1 depicts a simplifi ed schematic of the high frequency. These devices are fabricated on Linear amplifi er. The input stage is comprised of two differential Technology’s proprietary high speed complementary amplifi ers, a PNP stage Q1/Q2 and an NPN stage Q3/Q4 bipolar process. that are active over the different ranges of common mode input voltage. The PNP differential pair is active between the
Power Dissipation
negative supply to approximately 1.2V below the positive supply. As the input voltage moves closer toward the posi- The LT1800 amplifi er is offered in a small package, SOT-23, tive supply, the transistor Q5 will steer the tail current I which has a thermal resistance of 250°C/W, θ 1 to JA. So there is the current mirror Q6/Q7, activating the NPN differential a need to ensure that the die’s junction temperature should pair and the PNP pair becomes inactive for the rest of the not exceed 150°C. Junction temperature TJ is calculated input common mode range up to the positive supply. Also from the ambient temperature TA, power dissipation PD at the input stage, devices Q17 to Q19 act to cancel the bias and thermal resistance θJA: current of the PNP input pair. When Q1-Q2 are active, the TJ = TA + (PD • θJA) current in Q16 is controlled to be the same as the current in Q1-Q2, thus the base current of Q16 is nominally equal The power dissipation in the IC is the function of the sup- to the base current of the input devices. The base current ply voltage, output voltage and the load resistance. For of Q16 is then mirrored by devices Q17-Q19 to cancel the a given supply voltage, the worst-case power dissipation base current of the input devices Q1-Q2. PDMAX occurs at the maximum supply current and the V+ R3 R4 R5 V+ V– + + Q12 D1 ESDD1 ESDD2 Q11 Q13 Q15 I I 2 1 C2 +IN + D6 D8 Q5 VBIAS D2 I3 OUT D5 D7 CC V– –IN Q4 Q3 Q1 Q2 D3 ESDD4 ESDD3 BUFFER AND Q10 OUTPUT BIAS V+ V– D4 Q9 Q8 Q16 C1 Q17 Q18 Q19 Q7 Q6 Q14 R1 R2 V– 1800 F01
Figure 1. LT1800 Simplifi ed Schematic Diagram
1800fa 12