Datasheet AD8366 (Analog Devices) - 5

Data Sheet AD8366 PARALLEL AND SERIAL INTERFACE TIMING CS t t t 3 t4 1 2 SCLK t5 t6 X B-LSB B-MSB A-LSB SDAT A-MSB X
03 0 4-
SENB ALWAYS HIGH
58 07 Figure 2. SPI Port Timing Diagram
BIT[5:0] GAIN A GAIN B GAIN A, GAIN B DENA t t 9 10 DENB t7 t8 SENB
4-004
ALWAYS LOW
0758 Figure 3. Parallel Port Timing Diagram Rev. B | Page 5 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS PARALLEL AND SERIAL INTERFACE TIMING ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT DESCRIPTION INPUTS OUTPUTS OUTPUT DIFFERENTIAL OFFSET CORRECTION OUTPUT COMMON-MODE CONTROL GAIN CONTROL INTERFACE APPLICATIONS INFORMATION BASIC CONNECTIONS DIRECT CONVERSION RECEIVER DESIGN QUADRATURE ERRORS AND IMAGE REJECTION LOW FREQUENCY IMD3 PERFORMANCE BASEBAND INTERFACE CHARACTERIZATION SETUPS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE