Datasheet ADE7880 (Analog Devices) - 24

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ADE7880 Data Sheet POWER-UP PROCEDURE 3.3V – 10% D 2.0V ± 10% VD ADE7880 PSM0 READY 0V ~26ms ~40ms MICROPROCESSOR MAKES THE POR TIMER ADE7880 RSTDONE CHOICE BETWEEN
09
MICROPROCESSOR
0
SETS PM1 PIN TO 0; TURNED ON FULLY INTERRUPT I2C AND SPI
93-
APPLY VDD TO CHIP POWERED UP TRIGGERED
101 Figure 35. Power-Up Procedure The ADE7880 contains an on-chip power supply monitor that Immediately after entering PSM0 mode, all registers in the supervises the power supply (VDD). At power-up, the device is ADE7880 are set to their default values, including the inactive until VDD reaches 2.0 V ± 10%. When VDD crosses CONFIG2 and LPOILVL registers. this threshold, the power supply monitor keeps the device in the The ADE7880 signals the end of the transition period by pulling inactive state for an additional 26 ms to allow VDD to rise to the IRQ1 interrupt pin low and setting Bit 15 (RSTDONE) in 3.3 V − 10%, the minimum recommended supply voltage. the STATUS1 register to 1. This bit is cleared to 0 during the The PM0 and PM1 pins have internal pull-up resistors, but it is transition period and is set to 1 when the transition ends. necessary to set the PM1 pin to Logic 0, either through a micro- Writing the STATUS1 register with the RSTDONE bit set to 1 controller or by grounding the PM1 pin externally, before powering clears the status bit and returns the IRQ1 pin high. Because up the chip. The PM0 pin can remain open as it is held high, due RSTDONE is an unmaskable interrupt, Bit 15 (RSTDONE) in to the internal pull-up resistor. This ensures that the ADE7880 the STATUS1 register must be cancelled for the IRQ1 pin to always powers up in PSM0 (normal) mode. The time from the chip return high. Wait until the IRQ1 pin goes low before accessing being powered up completely to all functionality being enabled the STATUS1 register to test the state of the RSTDONE bit. At is about 40 ms (see Figure 35). It is necessary to ensure that the this point, as a good programming practice, cancel all other RESET pin is held high during the entire power-up procedure. status flags in the STATUS1 and STATUS0 registers by writing If PSM0 mode is the only desired power mode, the PM1 pin can the corresponding bits with 1. be tied to ground externally. When the ADE7880 enters PSM0 Initially, the DSP is in idle mode and, therefore, does not execute mode, the I2C port is the active serial port. To use the SPI port, any instructions. This is the moment to initialize all registers in toggle the SS/HSA pin three times from high to low. the ADE7880. See the Digital Signal Processor section for the To lock I2C as the active serial port, set Bit 1 (I2C_LOCK) of the proper procedure to initialize all registers and start the metering. CONFIG2 register to 1. From this moment, the device ignores If the supply voltage, VDD, falls lower than 2.0 V ± 10%, the spurious toggling of the SS/HSA pin, and a switch to the SPI ADE7880 enters an inactive state, which means that no port is no longer possible. measurements or computations are executed. If SPI is the active serial port, any write to the CONFIG2 register If the RESET pin is held low while the IC powers up or if the locks the port, and a switch to the I2C port is no longer possible. power-up sequence timing cannot be maintained as per To use the I2C port, the ADE7880 must be powered down or the Figure 35, perform the following sequence of write operations device must be reset by setting the RESET pin low. After the serial prior to starting the DSP (setting the RUN register to 0x01), to port is locked, the serial port selection is maintained when the ensure that the modulators are reset properly. device changes from one PSMx power mode to another. 1. 8-bit write: 0xAD is written at Address 0xE7FE. 2. 8-bit write: 0x14 is written at Address 0xE7E2. 3. Wait 200 μs. 4. 8-bit write: 0xAD is written at Address 0xE7FE. 5. 8-bit write: 0x04 is written at Address 0xE7E2. Rev. C | Page 24 of 107 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY POWER MANAGEMENT PSM0—NORMAL POWER MODE (ALL PARTS) PSM1—REDUCED POWER MODE PSM2—LOW POWER MODE PSM3—SLEEP MODE (ALL PARTS) POWER-UP PROCEDURE HARDWARE RESET SOFTWARE RESET FUNCTIONALITY THEORY OF OPERATION ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialiasing Filter ADC Transfer Function CURRENT CHANNEL ADC Current Waveform Gain Registers Current Channel HPF Current Channel Sampling di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR VOLTAGE CHANNEL ADC Voltage Waveform Gain Registers Voltage Channel HPF Voltage Channel Sampling CHANGING PHASE VOLTAGE DATA PATH POWER QUALITY MEASUREMENTS Zero-Crossing Detection Zero-Crossing Timeout Phase Sequence Detection Time Interval Between Phases Period Measurement Phase Voltage Sag Detection Sag Level Set Peak Detection Overvoltage and Overcurrent Detection Overvoltage and Overcurrent Level Set Neutral Current Mismatch PHASE COMPENSATION REFERENCE CIRCUIT DIGITAL SIGNAL PROCESSOR ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Offset Compensation Current Mean Absolute Value Calculation Current MAV Gain and Offset Compensation Voltage Channel RMS Calculation Voltage RMS Offset Compensation Voltage RMS in 3-Phase, 3-Wire Delta Configurations ACTIVE POWER CALCULATION Total Active Power Calculation Fundamental Active Power Calculation Managing Change in Fundamental Line Frequency Active Power Gain Calibration Active Power Offset Calibration Sign of Active Power Calculation Active Energy Calculation Integration Time Under Steady Load Active Energy Accumulation Modes Line Cycle Active Energy Accumulation Mode FUNDAMENTAL REACTIVE POWER CALCULATION Fundamental Reactive Power Gain Calibration Fundamental Reactive Power Offset Calibration Sign of Fundamental Reactive Power Calculation Fundamental Reactive Energy Calculation Integration Time Under Steady Load Fundamental Reactive Energy Accumulation Modes Line Cycle Reactive Energy Accumulation Mode APPARENT POWER CALCULATION Apparent Power Gain Calibration Apparent Power Offset Calibration Apparent Power Calculation Using VNOM Apparent Energy Calculation Integration Time Under Steady Load Apparent Energy Accumulation Modes Line Cycle Apparent Energy Accumulation Mode POWER FACTOR CALCULATION HARMONICS CALCULATIONS Harmonics Calcuations Theory Configuring the Harmonic Calculations Harmonic Calculations When a Phase is Monitored Harmonic Calculations When the Neutral is Monitored Configuring Harmonic Calculations Update Rate Recommended Approach to Managing Harmonic Calculations WAVEFORM SAMPLING MODE ENERGY-TO-FREQUENCY CONVERSION Synchronizing Energy Registers with CFx Outputs Energy Registers and CF Outputs for Various Accumulation Modes Sign of Sum of Phase Powers in the CFx Data Path NO LOAD CONDITION No Load Detection Based On Total Active Power and Apparent Power No Load Detection Based on Fundamental Active and Reactive Powers No Load Detection Based on Apparent Power CHECKSUM REGISTER INTERRUPTS Using the Interrupts with an MCU SERIAL INTERFACES Serial Interface Choice Communication Verification I2C-Compatible Interface I2C Write Operation I2C Read Operation I2C Read Operation of Harmonic Calculations Registers SPI-Compatible Interface SPI Read Operation SPI Read Operation of Harmonic Calculations Registers SPI Write Operation HSDC Interface ADE7880 QUICK SETUP AS ENERGY METER LAYOUT GUIDELINES CRYSTAL CIRCUIT ADE7880 EVALUATION BOARD DIE VERSION SILICON ANOMALY ADE7880 FUNCTIONALITY ISSUES FUNCTIONALITY ISSUES SECTION 1. ADE7880 FUNCTIONALITY ISSUES REGISTERS LIST OUTLINE DIMENSIONS ORDERING GUIDE