Datasheet ATtiny15L (Atmel) - 60

The device is clocked from the internal clock at the uncalibrated minimum frequency (0.8 - 1.6 MHz). The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 MCU clock cycles High: > 2 MCU clock cycles
Low-voltage Serial
When writing serial data to the ATtiny15L, data is clocked on the rising edge of SCK.
Programming Algorithm
When reading data from the ATtiny15L, data is clocked on the falling edge of SCK. See Figure 34, Figure 35, and Table 28 for timing details. To program and verify the ATtiny15L in the Serial Programming mode, the following sequence is recommended (See 4-byte instruction formats in Table 27): 1. Power-up sequence: Apply power between V and GND while RESET and SCK are set to “0”. If the pro- CC grammer cannot guarantee that SCK is held low during Power-up, RESET must be given a positive pulse of at least two MCU cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Program- ming Enable serial instruction to the MOSI (PB0) pin. Refer to the above section for minimum low and high periods for the serial clock input SCK. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issu- ing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a Chip Erase is performed (must be done to erase the Flash), wait t WD_ERASE after the instruction, give RESET a positive pulse, and start over from step 2. See Table 29 on page 63 for t value. WD_ERASE 5. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. An EEPROM memory location is first automatically erased before new data is written. Use data polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait t or t , respectively, before trans- WD_PROG_FL WD_PROG_EE mitting the next instruction. See Table 30 on page 63 for the t and WD_PROG_FL t values. In an erased device, no $FFs in the data file(s) need to be WD_PROG_EE programmed. 6. Any memory location can be verified by using the Read instruction, which returns the content at the selected address at the serial output MISO (PB1) pin. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn V power off. CC
60 ATtiny15L
1187H–AVR–09/07 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Analog Pins Internal Oscillators ATtiny15L Architectural Overview The General Purpose Register File The ALU - Arithmetic Logic Unit The Flash Program Memory The Program and Data Addressing Modes Register Direct, Single- register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing using the LPM Instruction Subroutine and Interrupt Hardware Stack The EEPROM Data Memory Memory Access and Instruction Execution Timing I/O Memory The Status Register - SREG Reset and Interrupt Handling ATtiny15L Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register - MCUSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Interrupt Handling Interrupt Response Time The General Interrupt Mask Register - GIMSK The General Interrupt Flag Register - GIFR The Timer/Counter Interrupt Mask Register - TIMSK The Timer/Counter Interrupt Flag Register - TIFR External Interrupt Pin Change Interrupt The MCU Control Register - MCUCR Sleep Modes Idle Mode ADC Noise Reduction Mode Power-down Mode Tuneable Internal RC Oscillator The System Clock Oscillator Calibration Register - OSCCAL Internal PLL for Fast Peripheral Clock Generation Timer/Counters The Timer/Counter0 Prescaler The Timer/Counter1 Prescaler The Special Function IO Register - SFIOR The 8-bit Timer/Counter0 The Timer/Counter0 Control Register - TCCR0 The Timer Counter 0 - TCNT0 The 8-bit Timer/Counter1 The Timer/Counter1 Control Register - TCCR1 The Timer/Counter1 - TCNT1 Timer/Counter1 Output Compare RegisterA - OCR1A Timer/Counter1 in PWM Mode Timer/Counter1 Output Compare RegisterB - OCR1B The Watchdog Timer The Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access The EEPROM Address Register - EEAR The EEPROM Data Register - EEDR The EEPROM Control Register - EECR Preventing EEPROM Corruption The Analog Comparator The Analog Comparator Control and Status Register - ACSR The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages Features Operation Prescaling and Conversion Timing ADC Noise Canceler Function The ADC Multiplexer Selection Register - ADMUX The ADC Control and Status Register - ADCSR The ADC Data Register - ADCL and ADCH ADLAR = 0 ADLAR = 1 Scanning Multiple Channels ADC Noise-canceling Techniques ADC Characteristics I/O Port B Unconnected Pins Alternative Functions of Port B The Port B Data Register - PORTB The Port B Data Direction Register - DDRB The Port B Input Pins Address - PINB PORT B as General Digital I/O Alternate Functions of Port B Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash High-voltage Serial Programming High-voltage Serial Programming Algorithm High-voltage Serial Programming Characteristics Low-voltage Serial Downloading Low-voltage Serial Programming Algorithm Data Polling Low-voltage Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics Typical Characteristics ATtiny15L Register Summary ATtiny15L Instruction Set Summary Ordering Information Packaging Information 8P3 8S2 Datasheet revision history Rev H - 09/07 Rev G - 06/07 Rev F - 06/05 Table of Contents